Someone asked in email:
I was trying to look at the picture from:
The receive chain transports the captured samples from ADC to the JESD Interface block, From there it goes to a buffer implemented on block rams from the FPGA fabric (util_adc_fifo); and from there to DMA, where it ultimately ends up in DDR.
How do I properly size the BRAM in the UTIL_ADC_FIFO and UTIL_DAC_FIFO?
Does it depend on sample rate or the FPGA I'm using?