I am trying to port the fmcjesdadc1 design to a design based on the Avnet UltraZed-7EV SOM (xczu7ev-fbvb900-1-i). I will be using only one GTH receive channel since our present carrier board has only an LPC FMC connector, but mainly I just want to get any JESD receiver design working before we start work on our next design version. I am having trouble figuring out how to configure the util_adxcvr core. I followed the instructions at https://wiki.analog.com/resources/fpga/docs/xgt_wizard and used the Ultrascale+ FPGA Transceiver Wizard. I am having trouble figuring out what settings to use for several instance attributes. For example, for "Rx Cdr Cfg" (72-bit value), "Rx Dfe Lpm Cfg" (16-bit value), and "Rx Pma Cfg" (22-bit value) I cannot find where these parameters exist in the gtwizard_ultrascale_v1_7_gthe4_channel.v or gtwizard_ultrascale_0_gthe4_channel_wrapper.v files. Maybe "Rx Pma Cfg" is the GTHE4_CHANNEL_PCIE_RXPMA_CFG parameter but this is only 16-bits wide in the generated Verilog files so I'm not sure. There are many GTHE4_CHANNEL_RXCDR_* parameters in the generated Verilog files but I don't know if or how they should be concatenated together into a single "Rx Cdr Cfg" value. There are others I'm unsure of too. Are there more detailed instructions for applying values found in the Verilog files generated by the transceiver wizard to the util_adxcvr instance?