AD9361 Filter Design: Low TX RF Bandwidth

Hi,

We are trying to design a filter that works at low sample rates and with low bandwidths. The LTE5 example filter design works really well for us, but we are trying to get a filter designed at <= 2MHz TX RF bandwidth, but so far we have not had any luck. Is there any guide we can follow to get a low frequency filter design working?

We are testing with two AD9361 in a null modem configuration through U-FL cables.

Any help will be greatly appreciated.

Thanks,

Sunip

Top Replies

  • 0
    •  Analog Employees 
    on Apr 14, 2021 4:12 PM in reply to sanjmehta

    The PFIR inside AD9361 may not be the best way to implement a rejection filter if that's what you are trying to do. If you can provide more info about what you need the filter to do an why its not working that would help.

    Note that the main purposes of the AD9361 PFIR are:

    1. Enable more decimation/interpolation so clocks can run at higher rates

    2. Provide passband equalization to reduce loss from HBs and ADC/DAC.

    -Travis

  • Hi Travis,

    We are using the QPSK HDL blocks from Transceiver Toolbox to communicate between two ADRV9361 SDRs. We need them to communicate at 2400 MHz LO, with an RF bandwidth of < 2 MHz (FCC license grants us 2 MHz RF bandwidth). We have tried simply setting the LO, Sampling rate and BW but the receiver is not receiving the signals from the transmitter. We have tried other filters (the LTE5, LTE20 examples, as well as custom filters for higher bandwidths) and with those we are transmitting and receiving just fine -- it's the lower bandwidth that has not worked so far, and we have no leads to how we can solve this issue. It is imperative that we get the system working at RF bandwidth of at most 2 MHz.

    Thanks,

    Sunip

  • 0
    •  Analog Employees 
    on Apr 14, 2021 5:48 PM in reply to sunipkm

    The modem design was never tested running that slow so you may run into pull-in range issues as they scale with sample rate.

    In regards to the filter, I doubt that is the issue unless:

    1. The bandwidth is too narrow for the waveform

    2. You are saturating (check the register map for status registers)

    3. The AGC is operating at a weird boundary.

    Case 3 is easy to check by putting the device into manual mode.

    -Travis

  • We tried to load the filter from here (iio-oscilloscope/LTE1p4_MHz.ftr at master · analogdevicesinc/iio-oscilloscope · GitHub) by writing the file to filter_fir_config, and enabling the filter by writing 1 to in_out_voltage_filter_fir_en. On dmesg, we see the following messages:

    ad9361 spi0.0: ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
    ad9361 spi0.0: ad9361_validate_enable_fir: Calculating filter rates failed -22 using min frequency
    ad9361 spi0.0: ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
    ad9361 spi0.0: ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
    ad9361 spi0.0: ad9361_validate_enable_fir: Calculating filter rates failed -22 using min frequency
    ad9361 spi0.0: ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit

    The receiver receives garbled messages.