Custom board with 2 AD9361 and problem with IODELAY GROUP

Hello, 

My team and I plan to connect our own RF board containing two AD9361 used only for their RX pins to a ZC706 platform. However compared to the FMCOMMS3 board in which each of the AD9361 is connected to a different FMC Connector, we use only one FMC connector. I used the design provided by AD for ZC706, but when I changed the pinouts to match my board (see enf of the post), I have the following error : 

I saw one of the topics that mentionned the patch : ad9361_iodelay_ctrl.patch and I did the modification described in it. But I ended up with this error : 

Can you please help me find a solution ?

Thanks in advance ! 

PS : Here is the pinout I used : 


# constraints
# ad9361

set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports h125_p] ; ## H4 FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports h125_n] ; ## H5 FMC_LPC_CLK0_M2C_N

set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G6 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G7 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D8 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D9 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H7 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H8 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G9 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_LPC_LA07_N

set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## C19 FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS25} [get_ports enable_1] ; ## C23 FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports txnrx_1] ; ## G27 FMC_LPC_LA25_P

set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[0]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[1]] ; ## G22 FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[2]] ; ## H25 FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[3]] ; ## H26 FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[0]] ; ## G24 FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[1]] ; ## G25 FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[2]] ; ## D23 FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## D24 FMC_LPC_LA23_N

set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## H31 FMC_LPC_LA28_P

set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## C22 FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N


# clocks


create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]

Parents Reply Children
  • In the files axi_ad9361_lvds_if.v and axi_ad9361_cmos_if.v I have the following code : 

    // receive data interface, ibuf -> idelay -> iddr

    genvar i;
    generate
    for (i = 0; i < 6; i = i + 1) begin: g_rx_data
    ad_data_in #(
    .DEVICE_TYPE (DEVICE_TYPE),
    .IODELAY_CTRL (0),
    .IODELAY_GROUP (IO_DELAY_GROUP))
    i_rx_data (
    .rx_clk (l_clk),
    .rx_data_in_p (rx_data_in_p[i]),
    .rx_data_in_n (rx_data_in_n[i]),
    .rx_data_p (rx_data_1_s[i]),
    .rx_data_n (rx_data_0_s[i]),
    .up_clk (up_clk),
    .up_dld (up_adc_dld[i]),
    .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
    .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
    .delay_clk (delay_clk),
    .delay_rst (delay_rst),
    .delay_locked ());
    end
    endgenerate

    // receive frame interface, ibuf -> idelay -> iddr

    ad_data_in #(
    .DEVICE_TYPE (DEVICE_TYPE),
    .IODELAY_CTRL (1),
    .IODELAY_GROUP (IO_DELAY_GROUP))
    i_rx_frame (
    .rx_clk (l_clk),
    .rx_data_in_p (rx_frame_in_p),
    .rx_data_in_n (rx_frame_in_n),
    .rx_data_p (rx_frame_s[1]),
    .rx_data_n (rx_frame_s[0]),
    .up_clk (up_clk),
    .up_dld (up_adc_dld[6]),
    .up_dwdata (up_adc_dwdata[34:30]),
    .up_drdata (up_adc_drdata[34:30]),
    .delay_clk (delay_clk),
    .delay_rst (delay_rst),
    .delay_locked (locked_s));

    // transmit data interface, oddr -> obuf

    generate
    for (i = 0; i < 6; i = i + 1) begin: g_tx_data
    ad_data_out #(
    .DEVICE_TYPE (DEVICE_TYPE),
    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
    .IODELAY_CTRL (0),
    .IODELAY_GROUP (IO_DELAY_GROUP))
    i_tx_data (
    .tx_clk (l_clk),
    .tx_data_p (tx_data_1[i]),
    .tx_data_n (tx_data_0[i]),
    .tx_data_out_p (tx_data_out_p[i]),
    .tx_data_out_n (tx_data_out_n[i]),
    .up_clk (up_clk),
    .up_dld (up_dac_dld[i]),
    .up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
    .up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
    .delay_clk (delay_clk),
    .delay_rst (delay_rst),
    .delay_locked ());
    end
    endgenerate

    // transmit frame interface, oddr -> obuf

    ad_data_out #(
    .DEVICE_TYPE (DEVICE_TYPE),
    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
    .IODELAY_CTRL (0),
    .IODELAY_GROUP (IO_DELAY_GROUP))
    i_tx_frame (
    .tx_clk (l_clk),
    .tx_data_p (tx_frame),
    .tx_data_n (tx_frame),
    .tx_data_out_p (tx_frame_out_p),
    .tx_data_out_n (tx_frame_out_n),
    .up_clk (up_clk),
    .up_dld (up_dac_dld[6]),
    .up_dwdata (up_dac_dwdata[34:30]),
    .up_drdata (up_dac_drdata[34:30]),
    .delay_clk (delay_clk),
    .delay_rst (delay_rst),
    .delay_locked ());

    So, I would say that the IODELAY_CTRL is set to 1 for one IP and to 0 for the other one. Is that correct ? 

  • 0
    •  Analog Employees 
    on Apr 13, 2021 10:49 AM in reply to Nadheema

    I was referring to the top level axi_ad9361 IP.   Since you have two AD9361 to interface you will need two axi_ad9361 cores.  Since these are on the same IO bank , in the block design where you instantiate your IPs one IP will have its IODELAY_CTRL set to 1 and the other to 0. 

    Laszlo

  • Actually, that's one of my problem. In the block diagram, I can see the two IPs, but I can't see where the IODELAY_CTRL have been set. When I double click the following IP block, I still can't set it.

    The design I use is the design provided by Analog Design and I am a bit lost in it... 

  • 0
    •  Analog Employees 
    on Apr 14, 2021 1:29 PM in reply to Nadheema

    Sorry, I was with the impression that you applied the follwoing patch /cfs-file/__key/communityserver-discussions-components-files/323/ad9361_5F00_iodelay_5F00_ctrl_5F00_2019.zip

    That should expose the IODELAY_CTRL as a parameter, so you can set it as described in the previous post. 

    Laszlo