AD9467 Native FMC Card / Xilinx Reference Desig

Hello, I am trying to use AD9467 Native FMC Card with ZC706. The software reference design is only available for KC705 and Zed board. Is there any reference design for ZC706 board?
Thanks in advance.

Top Replies

  • +2
    •  Analog Employees 
    on Apr 8, 2021 1:52 PM

    Hello,

    You should be able to port the Zed design to the ZC706 using https://wiki.analog.com/resources/fpga/docs/hdl/porting_project_quick_start_guide

    Regards,

    Adrian

  • Hello Adrian,

    Thank you so much!!!!

    I was trying to build the project manually using Vivado Tcl, but I got the following error after running "system_project.tcl"

    WARNING: [Coretcl 2-175] No Catalog IPs found
    ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell sys_i2c_mixer
    ERROR: [BD 5-7] Error: running create_bd_cell.
    ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
    "create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}"
    (procedure "ad_ip_instance" line 3)
    invoked from within
    "ad_ip_instance util_i2c_mixer sys_i2c_mixer"
    (file "C:/Users/eamon/Desktop/hdl-hdl_2018_r1/hdl-hdl_2018_r1/projects/common/zed/zed_system_bd.tcl" line 104)

    while executing
    "source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl"
    (file "system_bd.tcl" line 2)

    while executing
    "source system_bd.tcl"
    (procedure "adi_project_xilinx" line 97)
    invoked from within
    "adi_project_xilinx ad9467_fmc_zed"
    (file "system_project.tcl" line 6)

    Thanks in advance

    regards
    Prathosh 

     

  • +1
    •  Analog Employees 
    on Apr 12, 2021 10:23 AM in reply to Prathosh

    Hello Prathosh,

    We have a user guide regarding our HDL projects at:https://wiki.analog.com/resources/fpga/docs/hdl

    There is a section regarding how to build the project at: https://wiki.analog.com/resources/fpga/docs/build 

    If you use the make system, before building the project the libraries that are used in the project will be built. Otherwise, you need to either build them manually or use the steps described at "Xilinx auto TCL build" section (it may not be available in the 2018_R1 release, but it is available in the latest releases).

    Regards,

    Adrian

  • 0
    •  Analog Employees 
    on Apr 12, 2021 10:47 AM in reply to AdrianC

    moving this discussion to the appropriate forum

  • Hello Adrian,

    Thanks a lot, it did work. I followed the "Xilinx auto-build TCL" method. 

    1. So now I am able to get the zed board base design without any fail.

    2. I did follow https://wiki.analog.com/resources/fpga/docs/hdl/porting_project_quick_start_guide. to convert the zed base design to zc706.

    I am getting the following error causing the synthesis to fail

    [Synth 8-448] named port connection 'i2s_bclk' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":173]
    [Synth 8-448] named port connection 'i2s_lrclk' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":174]
    [Synth 8-448] named port connection 'i2s_mclk' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":175]
    [Synth 8-448] named port connection 'i2s_sdata_in' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":176]
    [Synth 8-448] named port connection 'i2s_sdata_out' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":177]
    [Synth 8-448] named port connection 'iic_fmc_scl_io' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":178]
    [Synth 8-448] named port connection 'iic_fmc_sda_io' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":179]
    [Synth 8-448] named port connection 'iic_mux_scl_i' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":180]
    [Synth 8-448] named port connection 'iic_mux_scl_o' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":181]
    [Synth 8-448] named port connection 'iic_mux_scl_t' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":182]
    [Synth 8-448] named port connection 'iic_mux_sda_i' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":183]
    [Synth 8-448] named port connection 'iic_mux_sda_o' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":184]
    [Synth 8-448] named port connection 'iic_mux_sda_t' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":185]
    [Synth 8-448] named port connection 'otg_vbusoc' does not exist for instance 'i_system_wrapper' of module 'system_wrapper' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":186]
    [Synth 8-6156] failed synthesizing module 'system_top' ["c:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/ad9467_fmc/zc706/system_top.v":38]
    [Common 17-83] Releasing license: Synthesis
    [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

    3. Therefore I commented on these ports in system_top.v, but in return, I got the following errors after synthesis

    • [Common 17-69] Command failed: 'P28' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":6]
    • [Common 17-69] Command failed: 'R22' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":8]
    • [Common 17-69] Command failed: 'V24' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":9]
    • [Common 17-69] Command failed: 'U24' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":10]
    • [Common 17-69] Command failed: 'R23' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":12]
    • [Common 17-69] Command failed: 'AA25' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":13]
    • [Common 17-69] Command failed: 'AE28' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":14]
    • [Common 17-69] Command failed: 'T23' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":15]
    • [Common 17-69] Command failed: 'AB25' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":16]
    • [Common 17-69] Command failed: 'T27' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":17]
    • [Common 17-69] Command failed: 'AD26' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":18]
    • [Common 17-69] Command failed: 'AB26' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":19]
    • [Common 17-69] Command failed: 'AA28' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":20]
    • [Common 17-69] Command failed: 'AC26' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":21]
    • [Common 17-69] Command failed: 'AE30' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":22]
    • [Common 17-69] Command failed: 'Y25' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":23]
    • [Common 17-69] Command failed: 'AA29' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":24]
    • [Common 17-69] Command failed: 'AD30' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":25]
    • [Common 17-69] Command failed: 'AC21' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":37]
    • [Common 17-69] Command failed: 'AJ14' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":41]
    • [Common 17-69] Command failed: 'AJ18' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":42]
    • [Common 17-69] Command failed: 'AC16' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":47]
    • [Common 17-69] Command failed: 'AC17' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":48]
    • [Common 17-69] Command failed: 'AJ13' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":49]
    • [Common 17-69] Command failed: 'AK25' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":50]
    • [Common 17-69] Command failed: 'R27' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":52]
    • [Common 17-69] Command failed: 'H14' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":59]
    • [Common 17-69] Command failed: 'J14' is not a valid site or package pin name. ["C:/Users/prath/Desktop/hdl-hdl_2019_r1/projects/common/zc706/zc706_system_constr.xdc":62]
    • [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open  
    • DRC
    • Pin Planning
    • IO Standard
    • [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs: gpio_bd[5] (LVCMOS15, requiring VCCO=1.500) and adc_clk_in_p (LVDS_25, requiring VCCO=2.500)
    • [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: gpio_bd[10] (LVCMOS15, requiring VCCO=1.500) and spi_sdio (LVCMOS25, requiring VCCO=2.500)
    • Netlist
    • Port
    • Required Buffer
    • [DRC RPBF-3] IO port buffering is incomplete: Device port iic_mux_scl[0] expects both input and output buffering but the buffers are incomplete.  
    4. I think these errors are due to the use of the wrong constraint files one in ~project/common/zc706/zc706_system_constr and one in project/ad9467/zc706/system_constr (Still using the zed board constraints file), if so how can I updates the current constraint file to zc706

    Thanks in advance, I appreciate your time.

    regards
    Prathosh T S