Hi,I am using the hdl release 'hdl_2019_r1'. And I am using the project in zc706 and EVAL-ADRV9008/9. And i am using no-os release '2019_R1'.
1. According to this thread ADRV9009 TX data width,"the data width of RX channel is 64bits=2(two channel)*16(data width per channel)*2(I/Q data format)."
I think it means that each of the 16 bit fifo_wr_data_x bus has one samples for the channel,like
adc_data_0 -> fifo_wr_data_0 is the I data for channel 0;
adc_data_1 -> fifo_wr_data_1 is the Q data for channel 0;
adc_data_2 -> fifo_wr_data_2 is the I data for channel 1;
adc_data_3 -> fifo_wr_data_3 is the Q data for channel 1;
Do i understand right?
2. The TX data width is 128bits, and split into four 32 bits bus,each of the 32 bits dac_data_x bus has two consecutive samples for the channel.
Does that means the throughput of TX is twice of RX ?