I am using the AD6676EVB with ZC706 eval board. I have run the reference deign in git hub successfully in vivado 2019.1 and obtained the ADC ramp data in DDR.
Further i wanted to configured the ADI AXI DMA Controller's output interface as AXI streaming interface in vivado and directly connected it to the RX stream interface of Xilinx AXI Streaming FIFO.
The DMA completes the transfer successfully which I checked by the TRANSFER COMPLETE status in DMA core but when i read the AXI STREAMING FIFO occupancy
status it shows 0 elements in the FIFO. The AXI Streaming FIFO has only RX stream interface enabled.
Alternatively i connected the ADI AXI DMA Controller's output interface as AXI streaming interface to the RX stream interface Xilinx AXI Streaming FIFO through a Xilinx Stream Interconnect.
Still the problem persists.