We recently purchased the AD-FMCDAQ2-EBZ along with Kintex platform.
I was going through the documentation in the AD Wiki site and came across the Receive specifications in the page given below:
The last graph is labelled as "SFDR sweep compared to Eval board with AD9523-1 reference clock".
Please clarify this point.
I believe that all the graphs shown are created with on-board AD9523-1 clock synthesiser.
I simulated the AD9523-1 in ADISIMClk and obtained a jitter of 220fs at 1GHz LVPECL output.
This is the worst jitter specification given in the Fig139 of datasheet.
Is there a better clock synthesizer available which can achieve a lower jitter specification.