AD9361 1R1T mode issue

Dear Folks,
I'd like to ask you for a hint regarding 1R1T mode on PicoZED (som adrv9361-z7035, with LVDS DDR interface). I read many threads on ez and I'm pretty sure I configured it properly.

I just cleared adi,2rx-2tx-mode-enable property of ad9361-phy device in the Linux driver and changed the property Mode 1r1t of axi_ad9361 IP core to 1 (as shown below).


In ILA, I analyzed the signals of axi_ad9361, which are responsible for ordering samples from user's IP core, TxFrame signal, as well as the lines which decide about the IP core clock in the original reference design (if it is l_clk/2 or l_clk/4).

The time domain for all ILA lines is set to l_clk. It appeared that the signals are incorrect. My detailed observations are as follows:
 
1. In 1R1T mode I guess the user IP core's samples should be ordereded every 2nd l_clk tick, not every 4th, as they are in my case. What is interesting, the Rx chain sample valid lines (adc_valid_i0, adc_valid_q0) seem to be correct for 1R1T mode.
2. The lines dac_r1_mode and adc_r1_mode should be pulled up (as they are necessary in the original reference design to properly select the user's IPcore clock).
3. The axi_ad9361 orders samples in both channels (note the changes of dac_valid_i1 line).

I'm using Vivado 2018.2. I modified the reference design so that my IP core generates samples on its own, without any request for DMA samples.

Could you, please, suggest what can be wrong with my settings?

Regards,
Matt