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Porting USRP E320 design to ADRV9361-z7035

Hello,


I am starting a project to make ADRV9361-z7035 SDR work with USRP E320 FPGA design instead of AD reference design. The motivation is that USRP hardware design bypasses ARM cores and hence is more reliable and supports strict timings. Also, E320 design uses SFP port and supports 1/10 Gbps rates which is necessary for our application.

E320 hardware is quite similar to the ADRV9361 and that makes it seem doable. They both have AD9361 RF chip, and the same SoC. USRP uses SFP port to send and receive data frames and there is one on the FMC carrier board.

However there are some differences that I am aware of. I would appreciate if anyone share any comments on these or share his experience if has done such a project before. Also if you could help me by clarifying any difference which you think I miss here that would be great.

These are the differences that I've found out so far:

1. E320's FPGA is XC7Z045 and ADRV's FPGA is XC7Z035 which is slightly smaller but the same family. I think I would only need to modify and build the Vivado project for the ADRV's FPGA part number: "xc7z035fbg676-2" instead of E320.

2. The packaging of the SoC is different, E320 is ffg900 but ADRV is fbg676. This needs modification on the pin mappings. Especially when it comes to GTX transceivers I have found some mismatches that needs work.

3. There is a 2GB DDR3 RAM dedicated for PL on E320 in addition to 1 GB DRAM for PS. I guess it is used for RFNoC blocks which I want to disable entirely. ADRV only has 1 GB DRAM connected to PS.

E320 FPGA design is here [https://github.com/EttusResearch/fpga/tree/UHD-3.15.LTS/usrp3/top/e320].

In the first step I only want to get the 1Gbps network mode through SFP working and totally bypass ARM cores.

thanks,

Samie


DRAM
[edited by: samiemostafavi at 1:32 PM (GMT -5) on 3 Mar 2021]
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