I am receiving data from observation channel of AD9371 that has 4 samples (4*16 = 64bit) in each clock cycle.
Would you please let me know if it is possible to have only 2 samples per clock cycle?
In the default reference design, it's not possible.
You could add an additional FIFO which does the conversion, on one side having device clock and 64bits and on the other another clock with double frequency and 32 bits.
The reference design uses 2 lanes for the observation links. One RF channel has I/Q, so in the default configuration you would have two samples per clock (2xI + 2xQ). Potentially you could use a single JESD204 lane, case in which you would end up with one sample per clock (1xI+1xQ), but this would require a hdl rebuild and device tree reconfiguration. Would also limit the maximum bandwidth of the observation channel.