FMCOMMS+ZCU102 WPWS/TPWS timing error


I'm trying to map the FMCOMMS2.ZCU102 design's Tx port to MPSOC's HD bank(Bank 44), the target outout cell is ODDRE1, which matches ADI's design(hdl/library/xilinx/common/ad_data_out.v), but somehow I'm getting WPWS timing errors, it complaints the pulse width is too short(expecting 8ns but get 4ns), the same design maps to HP bank doesn't have the problem, which remaped to OSERDES3 cell by the Vivado tool.

Any suggestion what should I do? use half rate clock instead of the 250MHz clock? I don't have the testbench to prove if the half rate clock is going to be function equivalent for the design.

Thanks for the help


| Design Timing Summary
| ---------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------
      0.315        0.000                      0                46839        0.010        0.000                      0                46769       -4.000      -32.000                       8                 20590

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