Using stream mode for Rx DMA on ADRV9009ZU11EG/ADRV2CRR

Hi mamad2

what did you connected to the other side of the AXI stream as a master? 

make sure if the SYNC_TRANSFER_START is set the tuser is driven high at some point.  Or set SYNC_TRANSFER_START  to zero.

Laszlo

Thanks Laszlo,

On the FIFO side, I connected s_axis_data and s_axis_valid to packed_fifo_wr_data and packed_fifo_wr_en respectively. 

lnagy said:

what did you connected to the other side of the AXI stream as a master? 

On the master side there would be one extra output called s_axis_xref_req that I leave it unconnected. Please let me know if this must be connected. 

lnagy said:

make sure if the SYNC_TRANSFER_START is set the tuser is driven high at some point.  Or set SYNC_TRANSFER_START  to zero.

I will make sure this flag is zero and try again and let you know.

mamad2 said:

I will make sure this flag is zero and try again and let you know.

DMA is in stream mode, I tried disabling SYNC_TRANSFER_START, connecting DMA valid and data signals as explained above. The data received is just zero for all Rxs.

Please let me know if other modifications are needed.  

make sure also the s_axis_last  signal is connected to zero. 

Can you share your DMA IP configuration/parameters? 

For reference you can run a simulation with DMAs to see how the AXI stream interface behaves: 

git clone https://github.com/ronagyl/hdl.git
git checkout system_tb
git submodule update --init --recursive
cd testbenches/dma_loopback
make MODE=gui

Laszlo

lnagy said:

make sure also the s_axis_last  signal is connected to zero.

Works fine with this, thanks for your help. One problem is that there is a missing data that I am thinking is due to Cyclic DMA mode of Tx. I already opened a question for that in the link below. 

https://ez.analog.com/microcontroller-no-os-drivers/f/q-a/539713/adrv9009-zu11eg-adrv2crr_fmc-missing-data-in-cyclic-dma-mode/401516#401516

Also, my purpose is to receive data from Rx1_A and Rx1_B that are 64 bits, so I modified the DMA bus width to 64 bits on input data and also the S_AXI_HP2_FPD port in the PS part to be 64 bits. For simplicity, I tried receiving data from Rx1_A and Rx2_A instead with following DMA configurations without modifying rx_CPACK block for now. Besides, I changed the command below to only active Rx1/Tx1.

talAction = TALISE_setRxTxEnable(pd, TAL_RX1_EN, TAL_TX1); 

As far as I know, once data with a size of Size_x is submitted to the DMA, it receives Size_x amount of data and then generates an interrupt. However, I captured a strange data as below and DMA still acting like the input/output data is 128bit. In the memory, samples of 4 Rx channels (128 bit) are appearing (although two of them are zeros) instead of 2. It looks like DMA is not realizing the inputs are now 64 bit. 

Would you please let me now how can I configure the DMA to work in 64 bits?