Documentation regarding implemenation of DDS (Transport layer) in FPGA Reference design.


I was wondering if there was any kind of documentation (or any reference) that I could follow to understand the implementation of the DDS core in the FPGA reference design? Unfortunately, Im a newbie and there are a lot of files related to the DDS in the design and its becoming incredibly confusing to follow for me, so apologies for that! 

Im running the 2019_R1 version on the a10soc + DAQ2. 

Any kind of information (even if vague) on the structure/architecture of the DDS implemented would be really really appreciated! 

Thank you so much for your time and hope you have a great day! 

Top Replies

  • +1
    •  Analog Employees 
    on Jan 15, 2021 1:50 PM 2 months ago


    Unfortunately, we only have documentation regarding the DDS at the level of a black box.
    You can control the frequency and the amplitude of the sine outputted by the DDS.
    What is your end goal for understanding the DDS? Maybe I can give you a few hints.
    There is a lot of documentation online regarding the principle of how a DDS works and you can find comments through out the code that can help you understand what is what...
    Click on expand regmap for the DAC Channel


  • Hello Andrei, 

    Really sorry about the late reply, unfortunately my health has not been keeping up with me. 

    Thank you so much for your reply, my main question was to see if there was any documentation about how the DDS is interfaced with the transport layer module. The reason I'm asking this question is because I'm trying to implement a frequency sweep (chirp) module in fabric, which interfaces with the transport layer

    Since the frequency sweep module I'm looking to make uses a multicore-DDS I wanted to see how the DDS is being implemented in the reference design, so that I could use that framework (mostly just the interface itself) and be able to place my module infront of the transport layer. Basically since I'm very new to the FPGA world, and this project is huge i just wanted a point of reference that I could look at in terms of connecting the module correctly to the transport layer. 

    With that in mind, I was wondering if there was anything you could point me to which could help me with this? How could I place my own module infront of the transport layer and disconnect the DMA, DDS etc. Most importantly, what are the ports I need to connect to (for example dac_ddata input) and what data format are the expecting. 

    Thank you so much for your time and effort! I really appreciate the support. 

    Warm Regards, 


  • The architecture image didn't come as clear as its supposed to be, this link should be better: 

  • 0
    •  Analog Employees 
    on Feb 22, 2021 8:01 AM 1 month ago in reply to URathore946

    Hi Udai,

    2. Sorry about the really basic question, but I just was wondering if you could elaborate a tiny bit more as to how I can add the mux. Should I add the mux as a part of my logic (and qsys IP) and control the mux using my regmap? If not, is there a more straight-forward solution that I am not seeing? (sorry for this question again)

    You have two options to multiplex your data:
    1.  create an IP (simple verilog code) that just selects the data source.
    2. export the signals you are working in the top(system_top.v) and do the selection there. Something like this:

    I exported those interfaces to the top, because I needed to get access to some speed signal.
    You can control the selection via a HPS GPIO or a switch on the board.

    3. This is more of a implementation question. Once I am able to finalize the hdl design using qsys, how do I go about testing this on the board? Sorry, but unfortunately I'm not familiar/comfortable with SOC/linux environment and I'm unsure as to what would be the easiest way to test/implement the design on board? I have a AXI4LITE interface connected to the HPS with a associated regmap. I've assigned the following address to it  (hopefully it is correct):

    Firs regenerate the programming files (.rbf and preloader image), than you can create a linux driver for your IP or you can simply use some tool like devmem2 to read and write from the registers of your IP.


  • Hello Andrei, 

    Thank you so so so much for all your feedback and support so far! Thanks to your help I was able to compile/build the entire project and generate the rbf file too. 

    Unfortunately, I'm unable to generate the preloader image. I was trying to follow the following tutorials:

    However, I was unable to generate the images using these tutorials. I think it may be because of a tool version mismatch : I'm using Quartus pro 19.3 and the same version of SoC EDS. Whenever I try to execute the command from the first link (Ive tried running it in both windows and ubuntu 18.04 LTS) : 

    bsp-create-settings --type uboot --bsp-dir software/uboot_bsp --preloader-settings-dir hps_isw_handoff --settings software/uboot_bsp/settings.bsp --set uboot.rbf_filename daq2_a10soc.rbf
    cd software/uboot_bsp/

    udai@udaiLinux:~/Desktop/my_project/Quartus-Project$ cd software/uboot_bsp/
    udai@udaiLinux:~/Desktop/my_project/Quartus-Project/software/uboot_bsp$ make
    Please visit for instructions on how to build the bootloader.

    I was wondering if there was any other documentation/resource I could follow that could take me from the quartus project to generating the necessary files? Would I also need to build the ADI linux kernel?  Even just the steps would be more than appreciated. 

    Or alternatively would you suggest changing tool versions? If so which tool version would you recommend? (In all honesty Im just trying to get this design to the board as easily/quickly as possible)

    Thank you so much once again for your help, support and feedback. It really helps me immensely. 

    Hope you have a great day! 



  • Also I wanted to add that running these commands does not generate the software\uboot_bsp\uboot-socfpga directory. So the second step in ( tutorial cannot be done. 


    Thank you once again! 



  • 0
    •  Analog Employees 
    on Mar 3, 2021 8:27 AM 1 month ago in reply to URathore946

    Hi Udai,

    What error messages do you get?

    I'm not exactly sure from which Quartus PRO( >20) version, Intel says that it no longer supports Windows builds for the preloader and that you also have to install separately the linaro gcc. Which can be installed after you install the SoC EDS in  <root install dir>/intelfpga_pro/20.1/embedded/host_tools/linaro/

    Or you can use quartus 18.1 standard, but you have to use the following environment variables:


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