I was wondering if there was any kind of documentation (or any reference) that I could follow to understand the implementation of the DDS core in the FPGA reference design? Unfortunately, Im a newbie and there are a lot of files related to the DDS in the design and its becoming incredibly confusing to follow for me, so apologies for that!
Im running the 2019_R1 version on the a10soc + DAQ2.
Any kind of information (even if vague) on the structure/architecture of the DDS implemented would be really really appreciated!
Thank you so much for your time and hope you have a great day!