Documentation regarding implemenation of DDS (Transport layer) in FPGA Reference design.

Hello, 

I was wondering if there was any kind of documentation (or any reference) that I could follow to understand the implementation of the DDS core in the FPGA reference design? Unfortunately, Im a newbie and there are a lot of files related to the DDS in the design and its becoming incredibly confusing to follow for me, so apologies for that! 

Im running the 2019_R1 version on the a10soc + DAQ2. 

Any kind of information (even if vague) on the structure/architecture of the DDS implemented would be really really appreciated! 

Thank you so much for your time and hope you have a great day! 

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  • +1
    •  Analog Employees 
    on Jan 15, 2021 1:50 PM 1 month ago

    Hi,

    Unfortunately, we only have documentation regarding the DDS at the level of a black box.
    You can control the frequency and the amplitude of the sine outputted by the DDS.
    What is your end goal for understanding the DDS? Maybe I can give you a few hints.
    There is a lot of documentation online regarding the principle of how a DDS works and you can find comments through out the code that can help you understand what is what...
    wiki.analog.com/.../axi_dac_ip
    Click on expand regmap for the DAC Channel

    Andrei 

  • Hello Andrei, 

    Really sorry about the late reply, unfortunately my health has not been keeping up with me. 

    Thank you so much for your reply, my main question was to see if there was any documentation about how the DDS is interfaced with the transport layer module. The reason I'm asking this question is because I'm trying to implement a frequency sweep (chirp) module in fabric, which interfaces with the transport layer https://ez.analog.com/fpga/f/q-a/538765/generating-a-chirp-sweep-signal-using-a10soc-and-fmc-daq2-boards

    Since the frequency sweep module I'm looking to make uses a multicore-DDS I wanted to see how the DDS is being implemented in the reference design, so that I could use that framework (mostly just the interface itself) and be able to place my module infront of the transport layer. Basically since I'm very new to the FPGA world, and this project is huge i just wanted a point of reference that I could look at in terms of connecting the module correctly to the transport layer. 

    With that in mind, I was wondering if there was anything you could point me to which could help me with this? How could I place my own module infront of the transport layer and disconnect the DMA, DDS etc. Most importantly, what are the ports I need to connect to (for example dac_ddata input) and what data format are the expecting. 

    Thank you so much for your time and effort! I really appreciate the support. 

    Warm Regards, 

    Udai

  • 0
    •  Analog Employees 
    on Feb 18, 2021 11:28 AM 17 days ago in reply to URathore946

    Hi Udai,

    I created  a wiki page for the DDS doc, I believe something went wrong when I tried to reply to this thread, because I can't find that reply.

    a) Kindly correct me if Im wrong, Based on your previous feedback, I believe the best option is to replace the util_ad9144_upack interface to axi_ad9144 with a multiplixer output or my freq. sweep module output. Just to confirm that would be this interface right (dac_ch_0 and dac_ch_1)? : 

    Yes, that is the interface... you don't have to replace, just add the multiplexer and your logic to it.generated

    . (I can see that in the AD reference design there is a DDS 64-bit output for each channel, does this mean that both channels are providing the same samples?)

    If the samples are generated by two separate DDS(one for each channel) than the samples of each analog output channel correspond to one dac channel in the FPGA. You can send the same samples to each channel if you want or you can disable that channel.

    a) dac_data_sync: 
         one of the inputs of the ad_dds.v (DDS) is the dac_data_sync, which I'm assuming is based on the external JESD sync signals: 

    Yes, this is an external signal, We use it to synchronize multiple systems(FPGAs) not the case of daq2.

    c) dac_dds_format input: what is the purpose of this input? 

    Take a  look at the registermap(dac channel) you will find it in one of the links in a previous discussion or in the wiki page described above.

    I will come back with a response regarding the dac_rst signal.


    Andrei

  • 0
    •  Analog Employees 
    on Feb 18, 2021 12:31 PM 17 days ago in reply to URathore946

    b) dac_rst signal:

    The dac_rst signal is being used in the up_xfer_cntrl (in up_dac_channel.v). I was wanting to use the up_xfer_cntrl module for transferring the control to data plane, however I'm unsure how to supply it the dac_rst signal due to the dac_rst's dependencies? Is the dac_rst driven by the AXI interface? 

    I'm not sure what are you trying to do here. Add a new register or use the REG_RSTN.
    Take a look at this example on how to add a new register using the up_xfer_cntrl, if this is what you are looking for.

    Andrei

  • Hello Andrei!

    Firstly, thank you so much for your quick reply, as always I'm incredibly grateful for all your feedback and support!! Thank you so much for creating the doc page! It is tremendously helpful, thank you so much!!

    Sorry I keep continuing this thread, its a one time thing, once I get a hang of the project+altera software I won't bother you anymore! 

    Thanks to your previous reply, I was able to complete the design and it seems to work fine for now. 

    To continue, my questions this time are a bit more quartus based: 

    1. Sorry i was not clear about my question, but your link actually helped me solve the problem. I was indeed trying to add my own regmap for controling the module, I just needed to figure out what to provide as dac_rst to up_xfer_cntrl since I dont have that signal. For now I've just pulled it down to 0 always. In any case, I think the diagram below would probably make my query + current architecture a bit easier to understand: 

    I'm not sure what are you trying to do here. Add a new register or use the REG_RSTN.
    Take a look at this example on how to add a new register using the up_xfer_cntrl, if this is what you are looking for.

        up_xfer_cntrl #(.DATA_WIDTH(81)) i_xfer_cntrl (
            .up_rstn (up_rstn),
            .up_clk (up_clk),
            .up_data_cntrl ({up_dac_dds_start_freq,
                            up_dac_dds_stop_freq,
                            up_dac_dds_step_word,
                            up_dac_dds_scale_1,
                            up_dac_dds_init_1,
                            up_dac_dds_format}),
            .up_xfer_done (),
            .d_rst (1'b0),
            .d_clk (link_clk),
            .d_data_cntrl ({start_freq_word,
                            stop_freq_word,
                            step_size_freq_word,
                            tone_1_scale,
                            tone_1_init_offset,
                            dac_dds_format}));

    2. Sorry about the really basic question, but I just was wondering if you could elaborate a tiny bit more as to how I can add the mux. Should I add the mux as a part of my logic (and qsys IP) and control the mux using my regmap? If not, is there a more straight-forward solution that I am not seeing? (sorry for this question again)

    Yes, that is the interface... you don't have to replace, just add the multiplexer and your logic to it

    3. This is more of a implementation question. Once I am able to finalize the hdl design using qsys, how do I go about testing this on the board? Sorry, but unfortunately I'm not familiar/comfortable with SOC/linux environment and I'm unsure as to what would be the easiest way to test/implement the design on board? I have a AXI4LITE interface connected to the HPS with a associated regmap. I've assigned the following address to it  (hopefully it is correct):

     

    sweep_module_0.altera_axi4lite_slave                0x0006_0000 - 0x0006_1fff

    I basically just want to know what are the steps (or if there is a tutorial) to bring this to the board in the easiest manner. If you could just point me in the right direction or provide a resource/example, that would be absolutely amazing and I would really appreciate it. 

    Once again, thank you so so so much for your support, feedback and help! 

    Hope you have a wonderful day! 

    Warm regards,

    Udai

  • The architecture image didn't come as clear as its supposed to be, this link should be better: 

  • 0
    •  Analog Employees 
    on Feb 22, 2021 8:01 AM 13 days ago in reply to URathore946

    Hi Udai,

    2. Sorry about the really basic question, but I just was wondering if you could elaborate a tiny bit more as to how I can add the mux. Should I add the mux as a part of my logic (and qsys IP) and control the mux using my regmap? If not, is there a more straight-forward solution that I am not seeing? (sorry for this question again)

    You have two options to multiplex your data:
    1.  create an IP (simple verilog code) that just selects the data source.
    2. export the signals you are working in the top(system_top.v) and do the selection there. Something like this:
    https://github.com/analogdevicesinc/hdl/blob/master/projects/cn0506_rgmii/a10soc/system_top.v#L339-L366

    https://github.com/analogdevicesinc/hdl/blob/master/projects/cn0506_rgmii/common/cn0506_qsys.tcl#L105-L108

    I exported those interfaces to the top, because I needed to get access to some speed signal.
    You can control the selection via a HPS GPIO or a switch on the board.

    3. This is more of a implementation question. Once I am able to finalize the hdl design using qsys, how do I go about testing this on the board? Sorry, but unfortunately I'm not familiar/comfortable with SOC/linux environment and I'm unsure as to what would be the easiest way to test/implement the design on board? I have a AXI4LITE interface connected to the HPS with a associated regmap. I've assigned the following address to it  (hopefully it is correct):

    Firs regenerate the programming files (.rbf and preloader image), than you can create a linux driver for your IP or you can simply use some tool like devmem2 to read and write from the registers of your IP.

    Andrei

Reply
  • 0
    •  Analog Employees 
    on Feb 22, 2021 8:01 AM 13 days ago in reply to URathore946

    Hi Udai,

    2. Sorry about the really basic question, but I just was wondering if you could elaborate a tiny bit more as to how I can add the mux. Should I add the mux as a part of my logic (and qsys IP) and control the mux using my regmap? If not, is there a more straight-forward solution that I am not seeing? (sorry for this question again)

    You have two options to multiplex your data:
    1.  create an IP (simple verilog code) that just selects the data source.
    2. export the signals you are working in the top(system_top.v) and do the selection there. Something like this:
    https://github.com/analogdevicesinc/hdl/blob/master/projects/cn0506_rgmii/a10soc/system_top.v#L339-L366

    https://github.com/analogdevicesinc/hdl/blob/master/projects/cn0506_rgmii/common/cn0506_qsys.tcl#L105-L108

    I exported those interfaces to the top, because I needed to get access to some speed signal.
    You can control the selection via a HPS GPIO or a switch on the board.

    3. This is more of a implementation question. Once I am able to finalize the hdl design using qsys, how do I go about testing this on the board? Sorry, but unfortunately I'm not familiar/comfortable with SOC/linux environment and I'm unsure as to what would be the easiest way to test/implement the design on board? I have a AXI4LITE interface connected to the HPS with a associated regmap. I've assigned the following address to it  (hopefully it is correct):

    Firs regenerate the programming files (.rbf and preloader image), than you can create a linux driver for your IP or you can simply use some tool like devmem2 to read and write from the registers of your IP.

    Andrei

Children
  • Hello Andrei, 

    Thank you so so so much for all your feedback and support so far! Thanks to your help I was able to compile/build the entire project and generate the rbf file too. 

    Unfortunately, I'm unable to generate the preloader image. I was trying to follow the following tutorials: 

    https://wiki.analog.com/resources/tools-software/linux-software/altera_soc_images

    https://wiki.analog.com/resources/tools-software/linux-build/generic/socfpga

    However, I was unable to generate the images using these tutorials. I think it may be because of a tool version mismatch : I'm using Quartus pro 19.3 and the same version of SoC EDS. Whenever I try to execute the command from the first link (Ive tried running it in both windows and ubuntu 18.04 LTS) : 

    bsp-create-settings --type uboot --bsp-dir software/uboot_bsp --preloader-settings-dir hps_isw_handoff --settings software/uboot_bsp/settings.bsp --set uboot.rbf_filename daq2_a10soc.rbf
    
    cd software/uboot_bsp/
    make

    udai@udaiLinux:~/Desktop/my_project/Quartus-Project$ cd software/uboot_bsp/
    udai@udaiLinux:~/Desktop/my_project/Quartus-Project/software/uboot_bsp$ make
    Please visit https://rocketboards.org/foswiki/Documentation/BuildingBootloader for instructions on how to build the bootloader.
    

    I was wondering if there was any other documentation/resource I could follow that could take me from the quartus project to generating the necessary files? Would I also need to build the ADI linux kernel?  Even just the steps would be more than appreciated. 

    Or alternatively would you suggest changing tool versions? If so which tool version would you recommend? (In all honesty Im just trying to get this design to the board as easily/quickly as possible)

    Thank you so much once again for your help, support and feedback. It really helps me immensely. 

    Hope you have a great day! 

    Regards,

    Udai

  • Also I wanted to add that running these commands does not generate the software\uboot_bsp\uboot-socfpga directory. So the second step in (https://wiki.analog.com/resources/tools-software/linux-software/altera_soc_images) tutorial cannot be done. 

     

    Thank you once again! 

    Regards,

    Udai

  • 0
    •  Analog Employees 
    on Mar 3, 2021 8:27 AM 4 days ago in reply to URathore946

    Hi Udai,

    What error messages do you get?

    I'm not exactly sure from which Quartus PRO( >20) version, Intel says that it no longer supports Windows builds for the preloader and that you also have to install separately the linaro gcc. Which can be installed after you install the SoC EDS in  <root install dir>/intelfpga_pro/20.1/embedded/host_tools/linaro/install_linaro.sh

    Or you can use quartus 18.1 standard, but you have to use the following environment variables:
    export ADI_IGNORE_VERSION_CHECK=1
    export QUARTUS_PRO_ISUSED=0

    https://rocketboards.org/foswiki/Documentation/SoCEDS#Install_SoC_EDS

    Andrei