ADRV9361-Z7035 reference design timeout errors with libiio example code

Hi all!

I strongly suspect that I'm missing something pretty basic here, so please feel free to tell me so if that's the case!

I'm working on a project that's going to involve modifying the ADRV9361-Z7035 reference hdl project from the Github repository (I'm using the master branch with Vivado 2019.1). It builds just fine with no timing errors (although there are some warnings, which I'm happy to provide if y'all think it's relevant), and I'm able to program the FPGA with no complaints.

However, when I try to run this simple example code as a sanity check to push and pull samples through the transceiver, I get a -110 (connection timed out) error code when the program polls the receiver buffer for samples, suggesting there's probably a timing issue somewhere. Notably, this example program runs just fine when I reboot the system, which of course programs the FPGA with the bitstream included in the boot image. I'm just using the Linux image provided from the ADRV936x RF SOM user guide, which I would've assumed came packaged with the same reference design that I cloned from the HDL repo, but clearly that's not the case.

I wasn't sure exactly what category to post this under, but I'm pretty sure this is an HDL design issue and not just a libiio issue. For more context, here's what bist_timing_analysis gives me with the boot image bitstream loaded:

And here's what I get when I program the reference design from the HDL repo from Vivado's Hardware Manager:

My assumption was that using provided example code with a provided reference design on a provided Linux image should work out of the box, but I expect that I've misinterpreted the purpose and proper use of at least one of these components and would very much appreciate someone putting me on the right path! Alternatively, if there's a way for me to access the Vivado project used to generate the bitstream included in the Linux boot image that I could work from instead of the image I got from the HDL repo, that seems like it would solve my problem too.

Thanks in advance for bearing with me as I figure this stuff out!

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