Clocking of DAQ2 (+KCU105) with Linux

Hi,

I am trying to change the sampling speed (both ADC and DAC) of a DAQ2 board mounted on a KCU105, running Linux on a Microblaze.

I followed this guide: https://wiki.analog.com/resources/eval/user-guides/ad-fmcdaq2-ebz/clocking

To rebuild the linux image I followed these instructions:

https://wiki.analog.com/resources/eval/user-guides/ad-fmcdaq2-ebz/software/linux/microblaze (version 20 Feb 2018 10:48)

The linux and hdl versions were:

analogdevicesinc/linux, branch master, commit hash: 74cdbe764db6b0a3442edfcabab042cadcb09719 (Nov 13 2020)

the hdl part was compiled with vivado 2019.1

analogdevicesinc/hdl, branch master, commit hash: ad4adddbe5cfa25f0084f2fb651b03f60c2f5857 (Oct 26 2020)

I tried different combinations of sampling speeds.

For some combinations the system works, (I can see a sine wave on the iio oscilloscope generated by the DAC), for others it doesn't:

ADC 1000 MHz - DAC 1000 MHz  ---> works (default settings)

ADC 600 MHz - DAC 600 MHz --> works (master clock divider=5, other dividers=(1,2,128,128))

ADC 333 MHz - DAC 333 MHz --> works (master clock divider=3, other dividers=(3,6,348,348))

---

ADC 750 MHz - DAC 750 MHz --> doesn't work (master clock divider=4, other dividers=(1,2,128,128))

ADC 375 MHz - DAC 375MHz --> doesn't work (master clock divider=4, other dividers=(2,4, 256, 256))

---

When it doesn't work, on the IIO oscilloscope the DAC part is not shown. In particular, on dmesg I get:

axi_adxcvr 44a60000.axi-ad9144-adxcvr: TX Error: 0
axi_adxcvr 44a60000.axi-ad9144-adxcvr: TX Error: 0
ad9144 spi0.1: Failed to enable JESD204 link: -5
ad9144: probe of spi0.1 failed with error -5

It seems that there is a problem with the JESD204 link.

The full dmesg for the (ADC 750 MHz - DAC 750 MHz) case is attached.

In order to change the master clock I'm using the following entry in the device tree (linux/arch/microblaze/boot/dts/adi-daq2.dtsi):

adi,pll2-m1-freq = <750000000>;

which is in the allowed range suggested.

/*
* Valid ranges based on VCO locking range:
* 980.00 MHz - 1033.33 MHz
* 735.00 MHz - 775.00 MHz
* 588.00 MHz - 620.00 MHz
*/
//

note: as reported in the list above (600 MHz) setting adi,pll2-m1-freq = <600000000> works fine.

Currently I'm interested in making the 750 MHz sampling speed work. Any suggestion?

750_750_dmesg.txt
Ramdisk addr 0x00000000, 
Compiled-in FDT at 0x8047479c
Linux version 4.19.0-g74cdbe7-dirty (a.rugliancich@pcw003x64) (gcc version 8.2.0 (crosstool-NG 1.20.0)) #20 Thu Dec 17 10:33:04 CET 2020
setup_memory: max_mapnr: 0x30000
setup_memory: min_low_pfn: 0x80000
setup_memory: max_low_pfn: 0xb0000
setup_memory: max_pfn: 0xb0000
Zone ranges:
  DMA      [mem 0x0000000080000000-0x00000000afffffff]
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000080000000-0x00000000ffffefff]
Initmem setup node 0 [mem 0x0000000080000000-0x00000000ffffefff]
On node 0 totalpages: 196608
  DMA zone: 1536 pages used for memmap
  DMA zone: 0 pages reserved
  DMA zone: 196608 pages, LIFO batch:63
setup_cpuinfo: initialising
setup_cpuinfo: Using full CPU PVR support
ERROR: Microblaze HW_MUL-different for PVR and DTS
wt_msr_noirq
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0 
Built 1 zonelists, mobility grouping on.  Total pages: 195072
Kernel command line: console=ttyUL0,115200
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 766128K/786432K available (4561K kernel code, 510K rwdata, 4416K rodata, 2888K init, 92K bss, 20304K reserved, 0K cma-reserved)
Kernel virtual memory layout:
  * 0xffffe000..0xfffff000  : fixmap
  * 0xffffe000..0xffffe000  : early ioremap
  * 0xb0000000..0xffffe000  : vmalloc & ioremap
NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
irq-xilinx: /amba_pl/interrupt-controller@41200000: num_irq=16, edge=0x410
/amba_pl/timer@41c00000: irq=1
clocksource: xilinx_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns
xilinx_timer_shutdown
xilinx_timer_set_periodic
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns
Calibrating delay loop... 49.35 BogoMIPS (lpj=246784)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
devtmpfs: initialized
random: get_random_u32 called from bucket_table_alloc.isra.6+0x1e8/0x218 with crng_init=0
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 256 (order: -1, 3072 bytes)
NET: Registered protocol family 16
jesd204: found 0 devices and 0 topologies
clocksource: Switched to clocksource xilinx_clocksource
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes)
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 512 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
random: fast init done
Skipping unavailable RESET gpio -2 (reset)
workingset: timestamp_bits=30 max_order=18 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
40600000.serial: ttyUL0 at MMIO 0x40600000 (irq = 5, base_baud = 0) is a uartlite
console [ttyUL0] enabled
brd: module loaded
Xilinx SystemACE device driver, major=254
xilinx_spi 44a70000.axi_quad_spi: no CS gpios available
libphy: Fixed MDIO Bus: probed
xilinx_axienet 40e00000.ethernet: TX_CSUM 2
xilinx_axienet 40e00000.ethernet: RX_CSUM 2
xilinx_axienet 40e00000.ethernet: missing/invalid xlnx,addrwidth property, using default
libphy: Xilinx Axi Ethernet MDIO: probed
i2c /dev entries driver
i2c i2c-0: Added multiplexed i2c bus 1
at24 2-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 2
i2c i2c-0: Added multiplexed i2c bus 3
i2c i2c-0: Added multiplexed i2c bus 4
pca954x 0-0075: registered 4 multiplexed busses for I2C mux pca9544
ad9523 spi0.0: spi0.0 supply vcc not found, using dummy regulator
ad9523 spi0.0: Linked as a consumer to regulator.0
ad9523 spi0.0: probed ad9523-1
axi_adxcvr 44a50000.axi-ad9680-adxcvr: AXI-ADXCVR-RX (17.01.a) using GTH3 at 0x44A50000 mapped to 0x(ptrval). Number of lanes: 4.
axi_adxcvr 44a60000.axi-ad9144-adxcvr: AXI-ADXCVR-TX (17.01.a) using GTH3 at 0x44A60000 mapped to 0x(ptrval). Number of lanes: 4.
NET: Registered protocol family 17
ad9680 spi0.2: AD9680 PLL LOCKED
axi_adxcvr 44a60000.axi-ad9144-adxcvr: TX Error: 0
axi_adxcvr 44a60000.axi-ad9144-adxcvr: TX Error: 0
ad9144 spi0.1: Failed to enable JESD204 link: -5
ad9144: probe of spi0.1 failed with error -5
cf_axi_adc 44a10000.axi-ad9680-hpc: ADI AIM (10.01.b) at 0x44A10000 mapped to 0x(ptrval), probed ADC AD9680 as MASTER
Freeing unused kernel memory: 2888K
This architecture does not have kernel memory protection.
Run /init as init process
random: dd: uninitialized urandom read (512 bytes read)
net eth0: Promiscuous mode disabled.
net eth0: Promiscuous mode disabled.
xilinx_axienet 40e00000.ethernet eth0: Link is Down
xilinx_axienet 40e00000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
random: dropbear: uninitialized urandom read (32 bytes read)
random: crng init done
# dmesg |packet_write_wait: Connection to 192.168.41.183 port 22: Broken pipe



minor edit: "Vivado 2019.1 branch master" --> "Vivado 2019.1"
[edited by: andrearu at 1:12 PM (GMT -5) on 2 Feb 2021]
Parents
  • 0
    •  Analog Employees 
    on Dec 21, 2020 3:06 PM 3 months ago

    Hello,

    It's possible that the QPLL is not in the correct range for the cases mentioned.

    If so, you need to regenerate the HDL design with the correct parameters for the use case by following the below guide:

    https://wiki.analog.com/resources/fpga/docs/xgt_wizard 

    Regards,

    Adrian

  • Hi,

    thanks for replying.

    So far I tried to use CPLL instead of QPLL for the AD9144 (DAC) chip by editing the block design.

    To do so, on the block design I selected axi_adxcvr_v1_0, and changed Qpll Enable to 0 (disabled) and "Sys Clk Sel" to "00" (CPLL). Then I regenerated the FPGA bistream successfully.

    On the device tree, I set my target frequency (linux/arch/microblaze/boot/dts/adi-daq2.dtsi)

    adi,pll2-m1-freq = <750000000>;

    and on linux/arch/microblaze/boot/dts/kcu105_fmcdaq2.dtts (changed lines in bold):

    axi_ad9144_adxcvr: axi-ad9144-adxcvr@44a60000 {
    compatible = "adi,axi-adxcvr-1.0";
    reg = <0x44a60000 0x10000>;

    clocks = <&clk0_ad9523 9>;
    clock-names = "conv";

    adi,sys-clk-select = <XCVR_CPLL>;
    adi,out-clk-select = <XCVR_REFCLK_DIV2>;
    adi,use-lpm-enable;
    adi,use-cpll-enable;

    #clock-cells = <1>;
    clock-output-names = "dac_gt_clk", "tx_out_clk";
    };

    with this configuration the JESD link with the ad9144 went up. The IIO oscilloscope now shows 750 MHz sample rate for both ADC and DAC.

    However, I noticed a strange side effect: now the ethernet inerface is unstable, it sometimes fails to get the IP from DCHP.

    At this point I also tried to change the dividers to get 375 MHz sample rate for both ADC and DAC (master=750, dividers=(2,4,256,256)). All JESD lines are ok (from dmesg), but the network interface (copper) never goes up. The problem is similar to the one reported here https://ez.analog.com/fpga/f/q-a/81127/fmcdaq2-kcu105-bitstream-with-functional-ethernet. DHCP fails, and also, e.g. "ifconfig eth0 <IP>" then "ping <other IP>" doesn't work.

    I find it strange that the QPLL/CPLL settings make the Ethernet part not work, because I think they are quite unrelated.

    I would appreciate any further suggestion about this issue.

  • 0
    •  Analog Employees 
    on Jan 8, 2021 2:53 PM 3 months ago in reply to andrearu

    Does your new design meet timing ? On the KCU105 the default design (without any evaluation board IP) has a tight timing margin .

  • Yes, the timing report (implementation) looks fine.

    timing

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