We have been working with ADRV9009 hdl design 2018_r2 with 100MHz profile.
Now I want to upgrade the design so that it can work at 400MHz profile.
It seem like ill have to re-build the hdl after updating few parameters like
set RX_OS_NUM_OF_CONVERTERS 2 ; # M
set RX_OS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
to get the ORx working at 400MHz.
As mentioned in this post https://ez.analog.com/fpga/f/q-a/162873/adrv9009-orx-at-491-52-msps/367710#367710
The issue is I am not able to find these parameters in common/adrv9009_bd.tcl
How can this be solved?