FMCDAQ2 Vivado adding clock

Hello all,

I want to add and route a clock signal from the ZYNQ IP. The only thing I am adding at this point is a new output clock on the ZYNQ IP, an ODDR block and an external clock. It is shown in the figure below:

But when I open the Elaborated design in Vivado in order to route this new output port to a pin in the board zc706, the next warning message appears:

 [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins *rst_async_d2_reg/PRE]'. [/home/jesus/baseline_code_2019/hdl/projects/daq2/zc706/daq2_zc706.srcs/sources_1/bd/system/xilinx/common/ad_rst_constr.xdc:7]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.

 [Common 17-55] 'set_property' expects at least one object. [/home/jesus/baseline_code_2019/hdl/projects/common/zc706/zc706_plddr3_constr.xdc:9]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

And the port is not and the newly generated port is not shown among the possible ports in the design (within the Elaborated Design). Even I tried to add the constraints for that port in the constraints file: zc706_plddr3_constr.xdc by adding the next two lines:

set_property PACKAGE_PIN AD18 [get_ports clk_out_0]
set_property IOSTANDARD LVCMOS33 [get_ports clk_out_0]

but in the end the change is not being taken into account.

Can anybody tell me how to change/add new stuff to the block design in Vivado? Am I missing something?

Thanks a lot!

Alex