Hello all,
I have a question related to the files in the hdl_2019_r1 branch.
I am following some other threads:
https://ez.analog.com/fpga/f/q-a/84684/10-mhz-reference-from-daq2-or-zc706
about how to generate and transmit a reference signal of 10MHz but there is no axi_ad9144_channel.v file in the latest release that I want to use.
Can you explain me why this file is missing? Could I add this file? Is there any other way to generate a reference signal and output that signal through a PMOD pin or an SMA of the zc706?
I am using also the fmcdaq2 board.
Thanks for your help!
Alex
Hello Alex,
In the 2019_r1 release we moved to a common transport layer for most JESD204 IPs. In that release we had a transition IP, which is a wrapper around the transport layer (https://wiki.analog…
In the 2019_r1 release we moved to a common transport layer for most JESD204 IPs. In that release we had a transition IP, which is a wrapper around the transport layer (https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac)
Regards,
Adrian