I first posted this question in high-speed ADC forum, yet was adviced to try here as well.
I'm trying to interface my fpga (ultrascale+) to some AD9675 chipsets (so JESD204b devices).
If I look at the example designs/projects, I get a bit confused, e.g. DAQ3 for zcu102 design:
- If I'm correct I guess you could call the util_adxcvr together with axi_adxcvr the instantiation of the high speed lanes
- then the receiving channels go ADI JESD204C receive axi interface and ADI JESD204 Receive IP: JESD204B PHY
- Then the signals from the PHY go to the JESD204 Transport layer for ADCs, why not use the AD9680 IP block here??
- The outgoing signals go to a cpack then to DMA.(as a fifo), yey in DAQ2 (zcu102) there's a separate ADC FIFO going to the DMA (here as a streaming interface).
- What's the difference (cpack to DMA FIFO vs CPACK to ADC FIFO to DMA stream), since both use the AD9680 IC and the same fpga?
For the AD9671/9675 design then, I think I need to copy step 1 and 2, yet alter the transportation layer with the AD9671 IP block.
The output of this IP block goes into a CPACK (8channels) then to DMA. Is this what's supposed to be the correct flow? In attach I have a picture of the IP blocks (for 2 lane setup)
Lots of thanks on any input!