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AD9671 based on DAQ2 and DAQ3 reference design

Hi all

I first posted this question in high-speed ADC forum, yet was adviced to try here as well.

I'm trying to interface my fpga (ultrascale+) to some AD9675 chipsets (so JESD204b devices). 

If I look at the example designs/projects, I get a bit confused, e.g. DAQ3 for zcu102 design:

  1. If I'm correct I guess you could call the util_adxcvr together with axi_adxcvr the instantiation of the high speed lanes
  2. then the receiving channels go ADI JESD204C receive axi interface and ADI JESD204 Receive IP: JESD204B PHY
  3. Then the signals from the PHY go to the JESD204 Transport layer for ADCs, why not use the AD9680 IP block here??
  4. The outgoing signals go to a cpack then to DMA.(as a fifo), yey in DAQ2 (zcu102) there's a separate ADC FIFO going to the DMA (here as a streaming interface).
    1. What's the difference (cpack to DMA FIFO vs CPACK to ADC FIFO to DMA stream), since both use the AD9680 IC and the same fpga?

For the AD9671/9675 design then, I think I need to copy step 1 and 2, yet alter the transportation layer with the AD9671 IP block.

The output of this IP block goes into a CPACK (8channels) then to DMA. Is this what's supposed to be the correct flow? In attach I have a picture of the IP blocks (for 2 lane setup)

Lots of thanks on any input!



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  • Yes, it the correct flow, but I would add a couple of remarks.

    First, the axi_adxcvr and util_adxcvr are the actual JESD204 PHY. What you called PHY is going to be the link layer, and the axi_ad9671 is the transport layer. For the transport layer please use the generic one instead. (

    In general you want to introduce  FIFO into your data path if the data rate is too high to be handled by the main memory interface. The FIFO will make it possible to save a bigger junk of continuous sample then offload to the main memory at a lower rate.



  • Hi

    thanks for the reply, it makes more sense already!

    Why is there a specific IP core in the hdl library if the generic is preferred?
    I was wondering, as we need 8 times the ADC for our project, I have to limit the amount of high speed lanes per ADC to 2 instead of the max, 4.

    This results in having an F of 8, in generic jesd, this is mentioned. Basically having two different clocks for the link layer and the transport layer. In the example pointed (git branch advr9009_less_lanes) there's an extra ADI IP: "ad_ip_jesd204_link_dnconv". This IP block I don't find in the future branches and the master. Has this been deprecated? Or can I still use this block?



  • "Why is there a specific IP core in the hdl library if the generic is preferred?" -  we introduced the generic IP recently, and there are still legacy code in the repo, it will be cleaned up in the future.

    can answer to your second question, he is more familiar with the ADRV9009 project.



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