Design tool Intel Quartus II, device model is A10gx,HDL version is GIthub HDL2018_R2, the software code is no-OS-2018_R2
The hardware changes are shown in the figure below. NCO is used with a sampling clock of 122.88mhz to generate a sine and cosine signal of 2M with a data bit width of 10bit. I think the sending clock is 61.44mhz and two 122.88m data are combined into 32bit, connected to Axi_adrv9009_dac_ch_*.The spectrum analyzer can only see the 2.0-g signal set in the software.
Sorry for the late reply. Do you still need help with this ?
If you are disconnecting the DMA and connecting your own source, from the software perspective you need to set the source as the DMA…
If you are disconnecting the DMA and connecting your own source, from the software perspective you need to set the source as the DMA:
https://wiki.analog.com/resources/fpga/docs/hdl/regmap ( 0x0106 0x0418 REG_CHAN_CNTRL_7 from DAC Channel section set to 0x2)