Hello Sergiu amiclaus AdrianC
I am working on adrv9361-z7035 and we want to route the signals internally from LVDS signal to LVCMOS25. Signals are 6pair of RX and 6pair of TX.
I am referring https://analog-staging.dw1.cosmocode.de/resources/eval/user-guides/ad-fmcomms2-ebz/introduction
this link. In this link there is one statement which is attached below.
1. How should we use Cmos mode on ADRV9361 P13 and P12 header?
2. Which bank we should use for routing signals from bank 35 to which bank?
3. Is this possible to route signals internally from bank 35 to bank 12 or bank 13? (LVDS to LVCMOS25)
Please reply as soon as possible.
Moved to FPGA Reference Designs.
Kindly reply as soon as possible.
"I am working on adrv9361-z7035 and we want to route the signals internally from LVDS signal to LVCMOS25." - sorry but I don't understand this.
Let's get back to the drawing board. :) What do you trying to do? In a high level? Which signals exactly and why you want to route them, and where?
Sorry for asking, but you and your colleges have created a dozens of threads with different description and info, and I'm getting confused. :)
PS. Please close all the other threads and let's continue the discussion here.
CsomI said:Let's get back to the drawing board. :) What do you trying to do? In a high level? Which signals exactly and why you want to route them, and where?
In the adrv9361-z7035, there are 6 pair of RX signals and 6 pair of TX signals(in the LVDS mode).
We have one another board (3.3V)we want to connect externally on P13 header of adrv9361-z7035. External board is operating on 3.3 V.
Adrv9361-z7035 RX and TX signals are going into Bank 35 and it is operating on 1.8V. So we have to route rx and tx signals internally from bank 35 to bank 12. For more specific we want 3.3V or 2.5V on P13 header.
For that we want to do LVDS(1.8V) to LVCOMS25(2.5V) conversion. I think with this information you are clear.
How could we do this for modifying system_top.v file?
Waiting for your response.
What do you want to connect to P13?