My customer is using:
ADI Linux repository branch id - 2019_R2 -
git repo link - https://urldefense.com/v3/__https://github.com/analogdevicesinc/linux.git__;!!A3Ni8CS0y2Y!tNRHy78tSWg0vxzwG1PRizWn1UvjRJVHoFX9oKcddpNsgwzwaJIWZ6mjGGjBLJC5-Q$ -
hdl repository branch id - 4972e5c42dfe7f0da8b8ce3c52083db142ed27a3 -
git repo link - https://urldefense.com/v3/__https://github.com/analogdevicesinc/hdl__;!!A3Ni8CS0y2Y!tNRHy78tSWg0vxzwG1PRizWn1UvjRJVHoFX9oKcddpNsgwzwaJIWZ6mjGGguGT9-Xg$ -
VIVADO 2019.1 to compile the adrv9009zu11eg project folder
They have build the adrv9009-zu11eg firmware from the hdl repository and add an debug ILA into PL.
The problem arises when they try to connect through the port JTAG, to the internal ILA to download some data.
What they observe is that the moment when the Hardware tool VIVADO Manager (2019) is started and activates the "hardware server" service on which, as soon as the JTAG connection with the board is established, causes the block, or the PS stops, and so also the relative sw that were in running at that time.
Sorry for the late reply.
In uEnv.txt on the boot partition can they make sure that the cpuidle.off=1 parameter is set ?
bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype…
Any feedback on this query.
bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait cpuidle.off=1
thanks a lot for your response.
They have update uEnv.txt and cpuidle.off=1 work fine thank you.
Is there a way for using JTAG workflow programming (withtout using SD boot) from xilinx command tool shell xsct ?
Yes, JTAG flow should work similarly with other Ultrascale FPGAs. We have a No-OS project for the board which is programmed through JTAG. Personally, I haven't used it recently, but my understanding is there is nothing that needs to be changed on the board for it to work, just make sure the SD card is not inserted.
For Linux, I don't think we have an example for running through JTAG.