adrv9009-zu11eg Project with ILA and JTAG

Hi

My customer is using:

ADI Linux repository branch id                   - 2019_R2 -

git repo link                                       - https://urldefense.com/v3/__https://github.com/analogdevicesinc/linux.git__;!!A3Ni8CS0y2Y!tNRHy78tSWg0vxzwG1PRizWn1UvjRJVHoFX9oKcddpNsgwzwaJIWZ6mjGGjBLJC5-Q$  -

hdl repository branch id                               - 4972e5c42dfe7f0da8b8ce3c52083db142ed27a3 -

git repo link                                                       - https://urldefense.com/v3/__https://github.com/analogdevicesinc/hdl__;!!A3Ni8CS0y2Y!tNRHy78tSWg0vxzwG1PRizWn1UvjRJVHoFX9oKcddpNsgwzwaJIWZ6mjGGguGT9-Xg$  -

VIVADO 2019.1 to  compile the adrv9009zu11eg project folder

 They have build the adrv9009-zu11eg firmware from the hdl repository and add an debug ILA into PL.

 The problem arises when they try to connect through the port JTAG, to the internal ILA to download some data.

 What they observe is that the moment when the Hardware tool VIVADO Manager (2019) is started and activates the "hardware server" service on which, as soon as the JTAG connection with the board is established, causes the block, or the PS stops, and so also the relative sw that were in running at that time.

  • Is there a way for this problem not to happen when you do connect with the JTAG?
  • Is there a way for using JTAG workflow programming from xilinx command tool shell ?

Thanks

IK

Danish