I am using an ADRV9009 board with ZC706 hardware. I am getting few failure messages during the first power ON. I am attaching the screenshot which has terminal prints for first power ON and second power ON. It always happens that when the board is power ON for first time after keeping it OFF for some time there are some failure messages. Is this normal? If so what is the reason for this?
The left side of the image is having the debug prints during the first power ON and the right side of the image is having debug prints for the second power ON.
No it is not normal. The board should initialize successfully even with the first boot up. Are you using eval board or custom board? After third power up, is the board initializing successfully? What is the SYNC status when you are seeing the issue?
Second power ON results is repeated from second power ON. It is only for first power ON that we are facing the issue. We are using eval board ADRV9009 and ZC706 Xilinx hardware.
Can you switch ON the board for sometime and then check if the board is initializing properly or not.
Also, make sure that you are following the power up sequence as mentioned in "SYSTEM INITIALIZATION" section in UG.
Moving to FPGA subspace for more comments.
Everything used is a reference design. What I see now is this is getting failed randomly during some power ON's. The Link status during the failed case is CGS. The SYNC status is asserted. I am not giving any external clock for this. What is the role of clock purity in this?