AD937x Rx ADC Triggered Capture with Tx Output (Tx-Rx Loop)

Hi,

I am using AD9375 platform with Zc706 utilizing the 2019-r1 hdl branch. I am looking for the ways for the Rx ADC triggering with the Tx outputs.  In other words: when a signal sent from transmitters, some trigger signal should reach to the ADC IPs to start data capture in the receivers. However, I could not find any example design to realize this idea although such trigger exists in the evaluation platform of the AD937x myknos (with the name tx_rx_loop trigger).  Do you have any example designs with this tx-rx triggering issue ? Which signal/outputs should or could be used in the hdl reference design to provide this rx capture triggering ?  

Thank you for your interest. 



Subject was changed
[edited by: HasanSatana at 1:32 PM (GMT -4) on 23 Oct 2020]
  • Sorry for the additional post, but I think with a figure it can be understood better. 

    In the attached file you can see our experiment with the tx-rx loop.  We transmit a signal continuosly at 700MHz, and receive the signal at the same frequency. We did this receive capturing 4 times, and each frames starting point is different. We basically want to get captures from the same point each receiving operation, so in the figure we want all lines (or peaks) to be aligned.  My actual question is  how could we modify  the reference HDL design to have such adc triggering ? 

  • +1
    •  Analog Employees 
    on Oct 23, 2020 5:43 PM in reply to HasanSatana

    This is no example code to do this with the open HDL from github.

    However, it's not that hard to implement. Basically, you need to control the dataflow from the TX DMA and to the RX DMA together. This could be done with an extra IP core that handles the enable/valid signals between the DMAs so that once the TX DMA start producing data, the RX DMA will allow data into its buffer.

    -Travis

  • Hi, thank you for the answer Travis. 

    Under the light of this information, I created a  basic module where I am giving a little bit longer version of the 'm_axis_xfer_req' signal from the tx_dma (which is asserted when I send a signal from tx and de-asserted after seeing m_axis_last signal )  to the fifo_wr_sync input of the rx_dma as a result:

    --> When I send a signal from tx,  rx-dma start capturing it to the memory. 

    Then after creating a boot.bin with this bit file, I am using the linux with this hdl configuration and python via the py-adi.

    After sending a signal using py-adi functions from transmitter I immediately use rx function (which creates an interrupt for the rx-dma), for data capture and I read the received signal, however I could not see a meaninful data for now in the receiver. 

    Am I missing something or should I check something else ? 

  • 0
    •  Analog Employees 
    on Dec 17, 2020 5:46 PM in reply to HasanSatana

    I would recommend feeding back data directly from TX to RX with the FPGA when debugging this design.

    Note that RX needs to be set up first before sending a transmit buffer. Otherwise, you will miss the transmitted sequence during the RX setup process.

    -Travis

  • Hi Travis,

    Now after your last suggestion I am able to send and receive signals in (cyclic buffer=false) situation with a specific fifo_wr_sync signal for the rx_dma.  I made 10 tx-rx loops and see the receving signal starts with very similar positions  but still it is not starting from a deterministic place. It is shifting 0 to 20 samples. I could not find what I am doing wrong. Here is what I did in the tx - rx loops.

    1) I first create a rx-buffer with the rx_init_channels() function in py-adi

    2) I transmit a signal (iio-push buffer),  As I start transmitting  the longer version of the dma-xfer-req signal is used to assert  the fifo_wr_sync input of the rx_dma block to be able to start filling the rx dma buffer.  

    3) Then using iio.refill and read command I look what I obtain at the receiver side.

    4) I destroy rx buffers.

    Side Note: Before I am doing all these,  I give rx_out_clk_0 clk  output as a clk input for  both of the ad9371_rx_clkgen and ad9371_tx_clkgen blocks to work in the same clk domain in tx and rx . I tried tx-rx loops with digital loopback as well but the results are the same.

    I wonder is there a component that gives a non-deterministic latency to the tx rx loop. In the tx side there are  dac-fifo, tx-upack,  tx-tpl and interpolator;  and rx side contains decimator, cpack fifo and  rx_tpl cores. What could I check or do as a next step ?

    Thanks for the suggestios.