ADC hardware timestamp in HDL and exposing iio timestamp channel

I have a working ADC HDL design, to which I would like to add the ability to time-stamp samples in hardware.

The output of the ADC core goes to a util_cpack module which packs IQ sample data from 4 channels. A 64bit hardware timestamp IP core module is update by the ADC clk and the timestamp is concatenated to the output of the cpack module and send to PL DDR3 via the ADC DMA controller on a Zynq-7 platform.

On the linux kernel side, I have a code fragment for the ADC driver that adds an IIO_CHAN_SOFT_TIMESTAMP(4) channel.

	[ID_AD6679] = {
		.name = "AD6679",
		.max_rate = 1250000000UL,
		.scale_table = ad6679_scale_table,
		.num_scales = ARRAY_SIZE(ad6679_scale_table),
		.num_channels = 5,
		.channel[0] = AD6679_CHAN(0, 0, 16, 'S', 0, NULL, 0),
		.channel[1] = AD6679_CHAN(1, 1, 16, 'S', 0, NULL, 0),
		.channel[2] = AD6679_CHAN(2, 2, 16, 'S', 0, NULL, 0),
		.channel[3] = AD6679_CHAN(3, 3, 16, 'S', 0, NULL, 0),
		.channel[4] = IIO_CHAN_SOFT_TIMESTAMP(4),

What is the recommend approach for:

  1. adding a hardware timestamp to ADC sample data in HDL
  2. retrieving the hardware timestamp from iio ?