AD937x DAC (Tx-1 and Tx-2) Outputs with Constant Delay (triggering tx2 with tx1)


In the reference HDL design there is no DAC triggering mechanism which is similar to evaluation design where there is EXT_SMA triggering  for both Tx1 and Tx2, as a result,  Tx1 and Tx2 outputs have always a fixed delay.

With the reference design  what we are trying to do is very similar, but we do not need to use an external trigger mechanism. We want that the Tx-2 output is created with the Tx-1 signal at the same time (triggered with Tx-1) so as to have a constant signal delay at the output in each transmission with both Tx1 and Tx2 enabled.

For this aim, we have tried to make common dac_valid inputs for the fir_interpolation stage. You can see the separate dac_valid inputs in the below figure before the fir_interpolation stage.( I have used dac_valid_0 also for the dac_valid_2 input , and used dac_valid_1  for the dac_valid_3 input.).  However,  I could not manage to have constant delay outputs. 


Instead of logic signals, maybe some kind of change is needed in the axi IPs below.

In other words, How can we obtain constant delayed -1 and Tx-2 outputs by basic triggering with Tx1 signal itself for the Tx2 output ? 

Thank you