I try to synchronize 2 ADRV9009 IC(4 TX and 4 RX) name as ADRV9009_1and ADRV9009_2 on single board.
I use ZYNQ7100 FPGA and clock IC to generate the two device_clk and two sysref signal to double ADRV9009, using the same clock IC to generate the ref_clk and sysref signal to FPGA.
The device_clk and sysref signal and ref_clk have the same phase.
The 12 steps to multiple_sync ADRV9009 has been running successfully with the right return value in the SDK with no-os project.
The device_clk of ADRV9009 is 122.88MHz and the sysref signal is 1.92MHz(122.88/64)，according to the reference of AD9528, I used the pulse mode of sysref signal.
In the fpga project, NO mmcm is used for the core clk of jesd204b core IP and jesd204b PHY IP, BUT the difference with the ADI reference project is that I am using the Xilinx jesd 204b core and xilinx jesd204b PHY ip.
After the initialization of double adrv9009 and FPAG, I got two situation of the phase difference, one is phase sync correction and the other is that ADRV9009_1 has one sample point difference with ADRV9009_2.
I have set value of F(the frame of jesd204b) as 4 and the value of K(multiple frame)as 32, after adjustment of lmfcOffset in the file of talise_config.c, I have got the safe LMFC boundary of jesd204b.
I'm confused about the difference of one sample point with double ADRV9009! What setting would cause this error?
Sorry for the late reply. Do you still need help with this ?
Do you use a single JESD204 link for both ADRV9009s?
Are the device_clock / sysref pairs length matched to ADRV9009s ?
Have you constrained the SYSREF and reference clock in the FPGA and does the system meet timing ?