zcu102/adrv9009 pl0 axi_clk changes

Hi there,

I have a design that I'm including the adrv9009/zcu102 reference design 2018.3.  I noticed that the axi_clk from the zynqmp pl0 changes from 99.99 to 103.42 MHz when linux boots.  I tested this by querying the clock rate before (while in uboot) and after the os boots.  I also confirmed this when launching a standalone application through sdk.  Can someone tell me where the OS is changing the pl0 clock rate?   Thanks!



Top Replies

    •  Analog Employees 
    Oct 23, 2020 in reply to mmedrano +1 suggested

    Hi ,

    So, if you are using 2018.3, I assume you are using this branch. What you are suggesting should work but it's should not be really necessary all of that. I would just extend the devicetree…