I am working on AD9371 project for some time now.
But I am unable to debug TX JESD properly.
My system has following version of design:
Non OS source codes 2019_R1
HDL design 2019_R1 (design migrated from kcu105 to kcu116)
Xilinx Board KCU116 (not a supported carrier board for AD9371)
TX JESD problem:
1. The KCU116 JESD is issued the K28.5 characters (BCBCBCBC) to AD9371 JESD.(It means that CGS phase is able to start)
2. SYSREF signal is able to reach both the sides (FPGA and AD9371 side)
3. AD9371 JESD issued SYNC signal to KCU116 JESD.
4. Then, KCU116 JESD is started ILAS phase.
However, the SYNC signal will be pulled low and stage will return to CGS stage.
5. I have done the trial multiple times and every time the status will be ILAS or CGS.
What I am possibly missing the points here?
Why does SYNC signal return to low in the middle of ILAS stage?
Debugging from my end:
I have cross verified the JESD configuration(lanes,octets and etc) on HDL side and Non OS sides.
I have considered the different frequencies for SYSREF alignment (Multiple of LMFC frequency)
Note: I will attach the ILA capture of TX JESD for reference (Line D : SYNC, Line D : SYSREF, Line F/H/J/L : Lane data)
Please your support is valuable
Added ILA capture files
[edited by: PHEGDE463 at 1:11 PM (GMT -4) on 1 Oct 2020]