ADRV9009-ZU11EG / FPGA 2xSYSREF and 2xREFCLK

Dear support team,

I see on the SOM clock architecture that FPGA receives from  HMC7044 a "2x REFCLK" and "2x SYSREF" signals.

Does it mean FPGA needs 2 distincts CLK signals + 2 distincts SYSREF signals? Why?

Thanks.

  • 0
    •  Analog Employees 
    on Oct 5, 2020 2:38 PM 1 month ago

    Hello,

    The reference clock can be used for both as they are in adjacent banks. In our reference design, we have used a reference clock per quad.

    For sysref and core_clk, we have paired Obs /TX and left RX to be controlled independently.

    Regards,

    Adrian

  • 0
    •  Analog Employees 
    on Oct 20, 2020 8:49 AM 1 month ago in reply to AdrianC

    Thanks

    If on a design, I have 2x ADRV9009 + 2x AD9695-1300 to get a 4R4T system.

    The 4x Rx data path are switched between both ADRV9009 and both AD9695 if more BW is required.

     I’m a bit lost regarding the number of HMC7044 outputs I need to build the clock tree of this system:

    1x sysref + 1xrefclk per ADRV9009 and AD9695 = 4xsysref + 4xrefclk

    But regarding the FPGA?

     on ADRV9009-ZU11EG block diagram: 6 signals are required for the FPGA. Is it enough in my case? Even if I have 2 additional AD9695?

  • 0
    •  Analog Employees 
    on Oct 20, 2020 9:05 AM 1 month ago in reply to descazot

    Given the AD9695 will probably have different JESD204 link parameters, for the FPGA you'll probably need 1 REF_CLK, 1 core_clk and one SYSREF for each of the links. In order for 1 REF_CLK to be enough per link, you need to make sure the ADRV9009s and the AD9695s are connected to adjacent banks of the FPGA.

    Regards,

    ADrian

  • Hi Adrian,

    I continue the same loop.

    Which could be the conditions in order to have only 1 core_clk and 2 sysref in the FPGA for explained case?

    We believe both ADRV9009 will be configured identically, same for both AD9695.

    On the other hand, 4 ref_clk are required, sure.

    It would be desirable to fulfill all clocking requirements with one HMC7044

  • 0
    •  Analog Employees 
    on Oct 21, 2020 1:30 PM 1 month ago in reply to jviniegra

    Hello,

    Do you know the lane rates for the ADRV9009 (RX/TX/ORx) and for the AD9695 ? You may be able to have 1 or 2 ref_clk, depending on the rates and the pin locations on the FPGA for the transceivers. 

    The core_clk needs to be lane rate / 40. If this is ok for RX/TX/ORx for ADRV9009 and AD9695, then you only need one. 

    If SYSREF can be source synchronous with core_clk and meet the requirements for JESD204, then you only need one for all links. 

    Depending on the FPGA family and jesd204 configuragion, you may be able to use one of the ref_clk also as core_clk.

    Regards,

    Adrian