I am working on ad9361 with zcu102. When I see valid and enable signals of DAC Upack IP CORE, dac_valid_out_0 signal behaves strangely. after It has been logic "1" first time, it turned logic "0" again. After while, it has been logic "1" again and it never falls "0" again.
Can you describe behavior of enable and valid signals of DAC Upack IP CORE and can you say that why dac_valid_out_0 behave like that ?
This discussion should continue at https://ez.analog.com/fpga/f/q-a/536329/behavior-of-signals-in-upack-ip-core/391350#391350.
Moved to FPGA Reference Designs.