Some ADCs such as the AD9684 have 4x DDC with virtual converter mapping.
If the AD9684 ADC has two physical channels and I enable 2 virtual converters in IQ mode, this should result in 4 individual voltage outputs for libiio and appear as voltage0, voltage1, voltage2 and voltage3 in iio-oscilloscope.
I would like to know where the virtual converter mapping done (e.g. in HDL or the Linux iio driver level) to make the invidual I and Q channel voltages available for iio-oscilloscope.
If I look at the HDL for a comparable ADC part, such as the AD9680 JESD204B part, in both the HDL and the linux iio driver, only 2 physical channels are enabled.
I'd like to know how data will be streamed and displayed on iio-oscilloscope if I enabled 2 DDC in complex mode, to make 4 voltage ouputs voltage0, voltage1, voltage2 and voltage3 to appear.
Hi,Sorry about this, because of the name 9684 I confused it with a JESD interface device.You have another open thread regarding this. Let's continue this discussion therehttps://ez.analog.com/fpga…
HI,To understand how things will be maped in HDL you can take a look at https://wiki.analog.com/resources/fpga/docs/hdl/generic_jesd_bds.Unfortunately our reference design does not yet have DDC support. You can configure the HDL and Linux, but as far as I know the IIO-Oscilloscope will not correctly display the waveforms.
DragosB can you confirm this?Andrei
The AD9684 is an LVDS part. Had it been a JESD204B part, yes, virtual converter mapping can be handled.
One option for me is to enable the AD9684 in LVDS byte mode and get it to operate with 2 DDCs with 4 virtual converters. If I have a solution for modifying the low-level axi_ad9684 core to expose 4 channels of data, that would be sufficient for my use.
Hi,Sorry about this, because of the name 9684 I confused it with a JESD interface device.You have another open thread regarding this. Let's continue this discussion therehttps://ez.analog.com/fpga/f/q-a/535481/hdl-ad9684-modifying-ip-core-for-lvds-byte-mode-operation
Sure, sounds good.