hdl: How to add ILA debug probes using script

I would like to know how to add an ILA debug probe to my HDL project using a tcl script.

I added the following lines to my system_project.tcl file, but the final design does not include an ila probe.

# enable/disable ila adc debug probes
set ila_adc_debug 1

if {$ila_adc_debug == 1} {

  ad_ip_instance ila ila_adc
  ad_ip_parameter ila_adc CONFIG.C_MONITOR_TYPE Native
  ad_ip_parameter ila_adc CONFIG.C_TRIGIN_EN false
  ad_ip_parameter ila_adc CONFIG.C_EN_STRG_QUAL 1
  ad_ip_parameter ila_adc CONFIG.C_NUM_OF_PROBES 7
  ad_ip_parameter ila_adc CONFIG.C_PROBE0_WIDTH 1
  ad_ip_parameter ila_adc CONFIG.C_PROBE1_WIDTH 1
  ad_ip_parameter ila_adc CONFIG.C_PROBE2_WIDTH 1
  ad_ip_parameter ila_adc CONFIG.C_PROBE3_WIDTH 32
  ad_ip_parameter ila_adc CONFIG.C_PROBE4_WIDTH 1
  ad_ip_parameter ila_adc CONFIG.C_PROBE5_WIDTH 1
  ad_ip_parameter ila_adc CONFIG.C_PROBE6_WIDTH 32

  ad_connect  axi_ad9684_core/adc_clk      ila_adc/clk
  ad_connect  axi_ad9684_core/adc_rst      ila_adc/probe0
  ad_connect  axi_ad9684_core/adc_valid_0  ila_adc/probe1
  ad_connect  axi_ad9684_core/adc_enable_0 ila_adc/probe2
  ad_connect  axi_ad9684_core/adc_data_0   ila_adc/probe3
  ad_connect  axi_ad9684_core/adc_valid_1  ila_adc/probe4
  ad_connect  axi_ad9684_core/adc_enable_1 ila_adc/probe5
  ad_connect  axi_ad9684_core/adc_data_1   ila_adc/probe6

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  • Hi Andrei,

    Here's what I did. I reinstalled the xilinx vivado cable drivers, once again.

    After that, I rebuilt the HDL project and the PetaLinux project. I copied over the BOOT.BIN file to the SD card. I have configured the system with a uEnv.txt to boot using TFTP and NFS root filesystem.

    I let the Linux kernel boot up, observed that the ADC has been successfully initialized and has an active clock, I proceed with putting the ADC in test mode. This can be done either using iio-oscilloscope or via command line by going into /sys/bus/iio/devices/iio:device1 typing the following command:

    # cd /sys/bus/iio/devices/iio:device
    # cat in_voltage_test_mode_available 
    off midscale_short pos_fullscale neg_fullscale checkerboard pn_long pn_short one_zero_toggle user ramp
    # echo one_zero_toggle > in_voltage0_test_mode
    # echo one_zero_toggle > in_voltage2_test_mode
    # cat in_voltage0_test_mode

    After that, I launched vivado and conntected to the target using the hardware manager and the debug ila_1 core appears. It is connected to adc_clk, so it is the correct clock domain.

    The only rationale that I kept in mind was that the ADC chip had to be initialized via software, for the adc_clk (data clock output dco) to start working, and then connect to the hardware target to debug it using the ila debug probe, because it will only be able to run, if the clock connected to it is running.

    If the ILA clock is connected to the PS FCLK0 or FCLK1, you will need to run software (no-OS or Linux) to initialize the Zynq PS side and get the clocks to start running before connecting to the FPGA target using Vivado. Just programming the FPGA with no software will not work.

    The only instance it will work is if you connect the ILA core to the FPGA boards external crystal oscillator as a clock source, using a board preset or the clocking wizard. Since the external clock will always run, the ILA core will be present when you directly program the FPGA board using JTAG without any software running on the Zynq PS side.