ZC706 with AD9136-FMC-EBZ Code Group Sync going in and out

Hi rdb9879

it looks there is a device tree available for the 9136 here: 

https://github.com/analogdevicesinc/linux/blob/master/arch/arm/boot/dts/zynq-zc706-adv7511-ad9136-fmc-ebz.dts

How did you build the hdl. what parameters did you used, what operation mode did you select for the JESD ? 

Thank you, 

Laszlo

I did see the device tree, but it's currently "not supported" and I couldn't figure out how to get it to build (I was given some instructions to try here: https://ez.analog.com/linux-software-drivers/f/q-a/167077/zc706-and-ad9136-how-to-include-reference-design-dtsi-file, but I couldn't figure it out). Thus, I went with bare metal CPU. For HDL, I built the analog devices "dac_fmc_ebz" reference design for the zc706 target. I configured the "config.tcl" to use JESD mode 11 set for device AD9136, single link mode, which should give these parameters:

M = 2

L = 8

S = 2

F = 1

HD = 1

N = 16

Np = 16

1. Toggling CGS state usually is caused by lane rate mismatch between Tx and Rx of the link. 

Check on the FPGA side  the QPLL frequency (f PLLClkout) and  TXOUT_DIV values. (see page 50 from 

https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf )

The DAC side looks good based on the register settings,  the expected lane rate is ref_clk x 40 = 5Gbps

2. I noticed you enabled lane polarity inversion in the 0x334 reg but it is already done in the hdl here :https://github.com/analogdevicesinc/hdl/blob/master/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl#L96

Laszlo

Thanks. You were exactly right.

Hello, I also find a similar problem. The sync signal kept going in and out. I checked the clock, channel, etc., and found no errors. I let FPGA send K28.5 all the time, and found that sync is also going in and out in the same way. May I ask what may be the cause of this problem? Thank you

Please can you open a thread with the setup you have ? 

Thanks, 

Laszlo

This is the phenomenon when sending normal data and K28.5

Hello, this is a PCB designed by myself. The parameters are:

DAC CLK: 500MHz

DAC sysref: 3.90625MHz

FPGA sysref: 3.90625MHz

FPGA gtxclk: 250MHz

And I use HMC7044 to generate the clock

///////////////////////////// AD9136 config /////////////////////////////
/*******************STEP 1: START UP THE DAC*******************/
{16bit ADDR, 8bit DATA}
assign reg_para[0] = {16'h0, 8'hA5};
assign reg_para[1] = {16'h0, 8'h24};
assign reg_para[2] = {16'h11, 8'h28};
assign reg_para[3] = {16'h80, 8'h0};
assign reg_para[4] = {16'h81, 8'h0};

assign reg_para[5] = {16'h12D, 8'h8B};
assign reg_para[6] = {16'h146, 8'h01};
assign reg_para[7] = {16'h2A4, 8'hFF};
assign reg_para[8] = {16'h232, 8'hFF};
assign reg_para[9] = {16'h333, 8'h01};

assign reg_para[10] = {16'h87, 8'h62};
assign reg_para[11] = {16'h88, 8'hC9};
assign reg_para[12] = {16'h89, 8'h0E};
assign reg_para[13] = {16'h8A, 8'h12};
assign reg_para[14] = {16'h8D, 8'h7B};

assign reg_para[15] = {16'h1B0, 8'h0};
assign reg_para[16] = {16'h1B9, 8'h24};
assign reg_para[17] = {16'h1BC, 8'h0D};
assign reg_para[18] = {16'h1BE, 8'h02};
assign reg_para[19] = {16'h1BF, 8'h8E};

assign reg_para[20] = {16'h1C0, 8'h2A};
assign reg_para[21] = {16'h1C1, 8'h2A};
assign reg_para[22] = {16'h1C4, 8'h7E};

assign reg_para[23] = {16'h8B, 8'h02}; //fDAC = 1G
assign reg_para[24] = {16'h8C, 8'h02}; //DAC PLL ref = 250M
assign reg_para[25] = {16'h85, 8'h08}; //Bcount = 8

assign reg_para[26] = {16'h1B5, 8'h09};
assign reg_para[27] = {16'h1BB, 8'h13};
assign reg_para[28] = {16'h1C5, 8'h06};

assign reg_para[29] = {16'h83, 8'h10};
assign reg_para[30] = {16'h84, 8'h01}; //read this Register, only 01 can continue

/*******************STEP 2: DIGITAL DATAPATH*******************/
assign reg_para[31] = {16'h112, 8'h0};
assign reg_para[32] = {16'h110, 8'h80};

/*******************STEP 3: TRANSPORT LAYER*******************/
assign reg_para[33] = {16'h200, 8'h0};
assign reg_para[34] = {16'h201, 8'h0};
assign reg_para[35] = {16'h300, 8'h08};
assign reg_para[36] = {16'h450, 8'h0};
assign reg_para[37] = {16'h451, 8'h0};

assign reg_para[38] = {16'h452, 8'h0};
assign reg_para[39] = {16'h453, 8'h83};
assign reg_para[40] = {16'h454, 8'h0};
assign reg_para[41] = {16'h455, 8'h1F};
assign reg_para[42] = {16'h456, 8'h0};

assign reg_para[43] = {16'h457, 8'h0F};
assign reg_para[44] = {16'h458, 8'h2F};
assign reg_para[45] = {16'h459, 8'h21};
assign reg_para[46] = {16'h45A, 8'h80};
assign reg_para[47] = {16'h45D, 8'h45};

assign reg_para[48] = {16'h46C, 8'hFF};
assign reg_para[49] = {16'h476, 8'h01};
assign reg_para[50] = {16'h47D, 8'hFF};

/*******************STEP 4: PHYSICAL LAYER*******************/
assign reg_para[51] = {16'h2AA, 8'hB7};
assign reg_para[52] = {16'h2AB, 8'h87};
assign reg_para[53] = {16'h2B1, 8'hB7};
assign reg_para[54] = {16'h2B2, 8'h87};
assign reg_para[55] = {16'h2A7, 8'h01};

assign reg_para[56] = {16'h2AE, 8'h01};
assign reg_para[57] = {16'h314, 8'h01};
assign reg_para[58] = {16'h230, 8'h08}; //lane rate is 5G
assign reg_para[59] = {16'h206, 8'h0};
assign reg_para[60] = {16'h206, 8'h1};

assign reg_para[61] = {16'h289, 8'h05}; //lane rate is 5G
assign reg_para[62] = {16'h284, 8'h62};
assign reg_para[63] = {16'h285, 8'hC9};
assign reg_para[64] = {16'h286, 8'h0E};
assign reg_para[65] = {16'h287, 8'h12};

assign reg_para[66] = {16'h28A, 8'h7B};
assign reg_para[67] = {16'h28B, 8'h0};
assign reg_para[68] = {16'h290, 8'h89};
assign reg_para[69] = {16'h294, 8'h24};
assign reg_para[70] = {16'h296, 8'h03};

assign reg_para[71] = {16'h297, 8'h0D};
assign reg_para[72] = {16'h299, 8'h02};
assign reg_para[73] = {16'h29A, 8'h8E};
assign reg_para[74] = {16'h29C, 8'h2A};
assign reg_para[75] = {16'h29F, 8'h78};

assign reg_para[76] = {16'h2A0, 8'h06};
assign reg_para[77] = {16'h280, 8'h01};
assign reg_para[78] = {16'h281, 8'h01}; // Verify that Bit 0 reads back high for SERDES PLL lock
assign reg_para[79] = {16'h268, 8'h62};

/*******************STEP 5: DATA LINK LAYER*******************/
assign reg_para[80] = {16'h301, 8'h01};
assign reg_para[81] = {16'h304, 8'h0};
assign reg_para[82] = {16'h305, 8'h0};
assign reg_para[83] = {16'h306, 8'h0A};
assign reg_para[84] = {16'h307, 8'h0A};

assign reg_para[85] = {16'h308, 8'h01}; //exchange line
assign reg_para[86] = {16'h309, 8'h13};
assign reg_para[87] = {16'h30A, 8'h3C};
assign reg_para[88] = {16'h30B, 8'h35};

assign reg_para[89] = {16'h03A, 8'h01};
assign reg_para[90] = {16'h03A, 8'h81};
assign reg_para[91] = {16'h03A, 8'hC1};
assign reg_para[92] = {16'h300, 8'h01};

assign reg_para[93] = {16'h470, 8'hFF}; //Acknowledge that four consecutive K28.5 characters have been detected on Lane 0 to Lane 3.
assign reg_para[94] = {16'h471, 8'hFF}; //Check for frame sync on all lanes.
assign reg_para[95] = {16'h472, 8'hFF}; //Check for good checksum.
assign reg_para[96] = {16'h473, 8'hFF}; //Check for ILAS.

///////////////////////////// AD9136 config /////////////////////////////


///////////////////////////// HMC7044 config /////////////////////////////
{16bit ADDR, 8bit DATA}
assign reg_para[0] = {16'h0, 8'h0};
assign reg_para[1] = {16'h1, 8'h60};
assign reg_para[2] = {16'h2, 8'h0};
assign reg_para[3] = {16'h3, 8'h36};
assign reg_para[4] = {16'h4, 8'h7f};
assign reg_para[5] = {16'h5, 8'h40};
assign reg_para[6] = {16'h6, 8'h0};
assign reg_para[7] = {16'h7, 8'h0};
assign reg_para[8] = {16'h9, 8'h1};
assign reg_para[9] = {16'ha, 8'h7};

assign reg_para[10] = {16'hb, 8'h7};
assign reg_para[11] = {16'hc, 8'h7};
assign reg_para[12] = {16'hd, 8'h7};
assign reg_para[13] = {16'he, 8'h7};
assign reg_para[14] = {16'h14, 8'he4};
assign reg_para[15] = {16'h15, 8'h0};
assign reg_para[16] = {16'h16, 8'hc};
assign reg_para[17] = {16'h17, 8'h0};
assign reg_para[18] = {16'h18, 8'h0};
assign reg_para[19] = {16'h19, 8'h0};

assign reg_para[20] = {16'h1a, 8'h8};
assign reg_para[21] = {16'h1b, 8'h0};
assign reg_para[22] = {16'h1c, 8'h4};
assign reg_para[23] = {16'h1d, 8'h1};
assign reg_para[24] = {16'h1e, 8'h4};
assign reg_para[25] = {16'h1f, 8'h1};
assign reg_para[26] = {16'h20, 8'h4};
assign reg_para[27] = {16'h21, 8'h4};
assign reg_para[28] = {16'h22, 8'h0};
assign reg_para[29] = {16'h26, 8'h10};

assign reg_para[30] = {16'h27, 8'h0};
assign reg_para[31] = {16'h28, 8'hf};
assign reg_para[32] = {16'h29, 8'h4};
assign reg_para[33] = {16'h2a, 8'h0};
assign reg_para[34] = {16'h31, 8'h1};
assign reg_para[35] = {16'h32, 8'h1};
assign reg_para[36] = {16'h33, 8'h1};
assign reg_para[37] = {16'h34, 8'h0};
assign reg_para[38] = {16'h35, 8'h32}; //clkin is 50M, VCO = 50M*50=2500M, Only use PLL2
assign reg_para[39] = {16'h36, 8'h0};

assign reg_para[40] = {16'h37, 8'hf};
assign reg_para[41] = {16'h38, 8'h18};
assign reg_para[42] = {16'h39, 8'h0};
assign reg_para[43] = {16'h3a, 8'h0};
assign reg_para[44] = {16'h3b, 8'h0};
assign reg_para[45] = {16'h46, 8'h0};
assign reg_para[46] = {16'h47, 8'h0};
assign reg_para[47] = {16'h48, 8'h8};
assign reg_para[48] = {16'h49, 8'h10};
assign reg_para[49] = {16'h50, 8'h2b};

assign reg_para[50] = {16'h51, 8'h32};
assign reg_para[51] = {16'h52, 8'h0};
assign reg_para[52] = {16'h53, 8'h0};
assign reg_para[53] = {16'h54, 8'h3};
assign reg_para[54] = {16'h5a, 8'h7};
assign reg_para[55] = {16'h5b, 8'h6};
assign reg_para[56] = {16'h5c, 8'h0};
assign reg_para[57] = {16'h5d, 8'h1};
assign reg_para[58] = {16'h64, 8'h0};
assign reg_para[59] = {16'h65, 8'h0};

assign reg_para[60] = {16'h70, 8'h8};
assign reg_para[61] = {16'h71, 8'h10};
assign reg_para[62] = {16'h78, 8'h8};
assign reg_para[63] = {16'h79, 8'h9};
assign reg_para[64] = {16'h7a, 8'ha};
assign reg_para[65] = {16'h7b, 8'h1};
assign reg_para[66] = {16'h7c, 8'hc};
assign reg_para[67] = {16'h7d, 8'hd};
assign reg_para[68] = {16'h7e, 8'he};
assign reg_para[69] = {16'h82, 8'hf};

assign reg_para[70] = {16'h83, 8'h0};
assign reg_para[71] = {16'h84, 8'h11};
assign reg_para[72] = {16'h85, 8'h0};
assign reg_para[73] = {16'h86, 8'h0};
assign reg_para[74] = {16'h8c, 8'h2};
assign reg_para[75] = {16'h8d, 8'h3};
assign reg_para[76] = {16'h8e, 8'h4};
assign reg_para[77] = {16'h8f, 8'h5};
assign reg_para[78] = {16'h91, 8'h6};
assign reg_para[79] = {16'h96, 8'h0};

assign reg_para[80] = {16'h97, 8'h0};
assign reg_para[81] = {16'h98, 8'h0};
assign reg_para[82] = {16'h99, 8'h0};
assign reg_para[83] = {16'h9a, 8'h0};
assign reg_para[84] = {16'h9b, 8'haa};
assign reg_para[85] = {16'h9c, 8'haa};
assign reg_para[86] = {16'h9d, 8'haa};
assign reg_para[87] = {16'h9e, 8'haa};
assign reg_para[88] = {16'h9f, 8'h55};
assign reg_para[89] = {16'ha0, 8'h56};

assign reg_para[90] = {16'ha1, 8'h97};
assign reg_para[91] = {16'ha2, 8'h3};
assign reg_para[92] = {16'ha3, 8'h0};
assign reg_para[93] = {16'ha4, 8'h0};
assign reg_para[94] = {16'ha5, 8'h0};
assign reg_para[95] = {16'ha6, 8'h1c};
assign reg_para[96] = {16'ha7, 8'h0};
assign reg_para[97] = {16'ha8, 8'h22};
assign reg_para[98] = {16'ha9, 8'h0};
assign reg_para[99] = {16'hab, 8'h0};

assign reg_para[100] = {16'hac, 8'h20};
assign reg_para[101] = {16'had, 8'h0};
assign reg_para[102] = {16'hae, 8'h8};
assign reg_para[103] = {16'haf, 8'h50};
assign reg_para[104] = {16'hb0, 8'h9};
assign reg_para[105] = {16'hb1, 8'hd};
assign reg_para[106] = {16'hb2, 8'h0};
assign reg_para[107] = {16'hb3, 8'h0};
assign reg_para[108] = {16'hb5, 8'h0};
assign reg_para[109] = {16'hb6, 8'h0};

assign reg_para[110] = {16'hb7, 8'h0};
assign reg_para[111] = {16'hb8, 8'h0};
assign reg_para[112] = {16'hc8, 8'hf3};
assign reg_para[113] = {16'hc9, 8'h80}; //sysref to fpga, f = 2500M / 640
assign reg_para[114] = {16'hca, 8'h2};
assign reg_para[115] = {16'hcb, 8'h0};
assign reg_para[116] = {16'hcc, 8'h0};
assign reg_para[117] = {16'hcd, 8'h0};
assign reg_para[118] = {16'hce, 8'h0};
assign reg_para[119] = {16'hcf, 8'h0};

assign reg_para[120] = {16'hd0, 8'h11};
assign reg_para[121] = {16'hd2, 8'hfd};
assign reg_para[122] = {16'hd3, 8'h0};
assign reg_para[123] = {16'hd4, 8'h3};
assign reg_para[124] = {16'hd5, 8'h0};
assign reg_para[125] = {16'hd6, 8'h0};
assign reg_para[126] = {16'hd7, 8'h0};
assign reg_para[127] = {16'hd8, 8'h0};
assign reg_para[128] = {16'hd9, 8'h0};
assign reg_para[129] = {16'hda, 8'h30};

assign reg_para[130] = {16'hdc, 8'hf3};
assign reg_para[131] = {16'hdd, 8'h5}; //CH2, DAC ref clock = 2500M / 5 = 500M
assign reg_para[132] = {16'hde, 8'h0};
assign reg_para[133] = {16'hdf, 8'h0};
assign reg_para[134] = {16'he0, 8'h0};
assign reg_para[135] = {16'he1, 8'h0};
assign reg_para[136] = {16'he2, 8'h0};
assign reg_para[137] = {16'he3, 8'h0};
assign reg_para[138] = {16'he4, 8'h11};
assign reg_para[139] = {16'he6, 8'hfd};

assign reg_para[140] = {16'he7, 8'h80}; //CH3, DAC sysref = 2500M / 640
assign reg_para[141] = {16'he8, 8'h2};
assign reg_para[142] = {16'he9, 8'h0};
assign reg_para[143] = {16'hea, 8'h0};
assign reg_para[144] = {16'heb, 8'h0};
assign reg_para[145] = {16'hec, 8'h0};
assign reg_para[146] = {16'hed, 8'h0};
assign reg_para[147] = {16'hee, 8'h30};
assign reg_para[148] = {16'hf0, 8'hf3};
assign reg_para[149] = {16'hf1, 8'h6};

assign reg_para[150] = {16'hf2, 8'h0};
assign reg_para[151] = {16'hf3, 8'h0};
assign reg_para[152] = {16'hf4, 8'h0};
assign reg_para[153] = {16'hf5, 8'h0};
assign reg_para[154] = {16'hf6, 8'h0};
assign reg_para[155] = {16'hf7, 8'h0};
assign reg_para[156] = {16'hf8, 8'h11};
assign reg_para[157] = {16'hfa, 8'hf5};
assign reg_para[158] = {16'hfb, 8'h0};
assign reg_para[159] = {16'hfc, 8'h3};

assign reg_para[160] = {16'hfd, 8'h0};
assign reg_para[161] = {16'hfe, 8'h0};
assign reg_para[162] = {16'hff, 8'h0};
assign reg_para[163] = {16'h100, 8'h0};
assign reg_para[164] = {16'h101, 8'h0};
assign reg_para[165] = {16'h102, 8'h30};
assign reg_para[166] = {16'h104, 8'hf3};
assign reg_para[167] = {16'h105, 8'h6};
assign reg_para[168] = {16'h106, 8'h0};
assign reg_para[169] = {16'h107, 8'h0};

assign reg_para[170] = {16'h108, 8'h0};
assign reg_para[171] = {16'h109, 8'h0};
assign reg_para[172] = {16'h10a, 8'h0};
assign reg_para[173] = {16'h10b, 8'h0};
assign reg_para[174] = {16'h10c, 8'h11};
assign reg_para[175] = {16'h10e, 8'hfd};
assign reg_para[176] = {16'h10f, 8'h0};
assign reg_para[177] = {16'h110, 8'h3};
assign reg_para[178] = {16'h111, 8'h0};
assign reg_para[179] = {16'h112, 8'h0};

assign reg_para[180] = {16'h113, 8'h0};
assign reg_para[181] = {16'h114, 8'h0};
assign reg_para[182] = {16'h115, 8'h0};
assign reg_para[183] = {16'h116, 8'h30};
assign reg_para[184] = {16'h118, 8'hf3};
assign reg_para[185] = {16'h119, 8'h6};
assign reg_para[186] = {16'h11a, 8'h0};
assign reg_para[187] = {16'h11b, 8'h0};
assign reg_para[188] = {16'h11c, 8'h0};
assign reg_para[189] = {16'h11d, 8'h0};

assign reg_para[190] = {16'h11e, 8'h0};
assign reg_para[191] = {16'h11f, 8'h0};
assign reg_para[192] = {16'h120, 8'h11};
assign reg_para[193] = {16'h122, 8'hfd};
assign reg_para[194] = {16'h123, 8'h0};
assign reg_para[195] = {16'h124, 8'h3};
assign reg_para[196] = {16'h125, 8'h0};
assign reg_para[197] = {16'h126, 8'h0};
assign reg_para[198] = {16'h127, 8'h0};
assign reg_para[199] = {16'h128, 8'h0};

assign reg_para[200] = {16'h129, 8'h0};
assign reg_para[201] = {16'h12a, 8'h30};
assign reg_para[202] = {16'h12c, 8'hf3};
assign reg_para[203] = {16'h12d, 8'ha}; //CH10, gtx clk0 = 2500M / 10 = 250M
assign reg_para[204] = {16'h12e, 8'h0};
assign reg_para[205] = {16'h12f, 8'h0};
assign reg_para[206] = {16'h130, 8'h0};
assign reg_para[207] = {16'h131, 8'h0};
assign reg_para[208] = {16'h132, 8'h0};
assign reg_para[209] = {16'h133, 8'h0};

assign reg_para[210] = {16'h134, 8'h11};
assign reg_para[211] = {16'h136, 8'hf3};
assign reg_para[212] = {16'h137, 8'h80}; //CH11 50 divide, cc0
assign reg_para[213] = {16'h138, 8'h2};
assign reg_para[214] = {16'h139, 8'h0};
assign reg_para[215] = {16'h13a, 8'h0};
assign reg_para[216] = {16'h13b, 8'h0};
assign reg_para[217] = {16'h13c, 8'h0};
assign reg_para[218] = {16'h13d, 8'h0};
assign reg_para[219] = {16'h13e, 8'h30};

assign reg_para[220] = {16'h140, 8'hf3};
assign reg_para[221] = {16'h141, 8'ha}; //CH12 20 divide, gtx clk1 = 2500M / 10 = 250M
assign reg_para[222] = {16'h142, 8'h0};
assign reg_para[223] = {16'h143, 8'h0};
assign reg_para[224] = {16'h144, 8'h0};
assign reg_para[225] = {16'h145, 8'h0};
assign reg_para[226] = {16'h146, 8'h0};
assign reg_para[227] = {16'h147, 8'h0};
assign reg_para[228] = {16'h148, 8'h11};
assign reg_para[229] = {16'h14a, 8'hf3};

assign reg_para[230] = {16'h14b, 8'h80}; //CH13 640 divide, cc2
assign reg_para[231] = {16'h14c, 8'h2};
assign reg_para[232] = {16'h14d, 8'h9};
assign reg_para[233] = {16'h14e, 8'h0};
assign reg_para[234] = {16'h14f, 8'h0};
assign reg_para[235] = {16'h150, 8'h0};
assign reg_para[236] = {16'h151, 8'h0};
assign reg_para[237] = {16'h152, 8'h30};

assign reg_para[238] = {16'h1, 8'h62};
assign reg_para[239] = {16'h1, 8'h60};

///////////////////////////// HMC7044 config /////////////////////////////

///////////////////////////// JESD204 AXI config /////////////////////////////

write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x008, 0x00000001);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x00C, 0x00000001);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x010, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x014, 0x00000003);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x018, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x020, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x024, 0x0000001F);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x028, 0x000000FF);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x02C, 0x00000001);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x80C, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x810, 0x000F0F01);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x814, 0x00010101);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x818, 0x00000000);

///////////////////////////// JESD204 AXI config /////////////////////////////

When FPGA keeps sending K28.5, it will also find sync going in and out, I tried to change lanerate(10G, 3G), but it also didn't work. Thank you!

Hello, this is a PCB designed by myself. The parameters are:

DAC CLK: 500MHz

DAC sysref: 3.90625MHz

FPGA sysref: 3.90625MHz

FPGA gtxclk: 250MHz

And I use HMC7044 to generate the clock

///////////////////////////// AD9136 config /////////////////////////////
/*******************STEP 1: START UP THE DAC*******************/
{16bit ADDR, 8bit DATA}
assign reg_para[0] = {16'h0, 8'hA5};
assign reg_para[1] = {16'h0, 8'h24};
assign reg_para[2] = {16'h11, 8'h28};
assign reg_para[3] = {16'h80, 8'h0};
assign reg_para[4] = {16'h81, 8'h0};

assign reg_para[5] = {16'h12D, 8'h8B};
assign reg_para[6] = {16'h146, 8'h01};
assign reg_para[7] = {16'h2A4, 8'hFF};
assign reg_para[8] = {16'h232, 8'hFF};
assign reg_para[9] = {16'h333, 8'h01};

assign reg_para[10] = {16'h87, 8'h62};
assign reg_para[11] = {16'h88, 8'hC9};
assign reg_para[12] = {16'h89, 8'h0E};
assign reg_para[13] = {16'h8A, 8'h12};
assign reg_para[14] = {16'h8D, 8'h7B};

assign reg_para[15] = {16'h1B0, 8'h0};
assign reg_para[16] = {16'h1B9, 8'h24};
assign reg_para[17] = {16'h1BC, 8'h0D};
assign reg_para[18] = {16'h1BE, 8'h02};
assign reg_para[19] = {16'h1BF, 8'h8E};

assign reg_para[20] = {16'h1C0, 8'h2A};
assign reg_para[21] = {16'h1C1, 8'h2A};
assign reg_para[22] = {16'h1C4, 8'h7E};

assign reg_para[23] = {16'h8B, 8'h02}; //fDAC = 1G
assign reg_para[24] = {16'h8C, 8'h02}; //DAC PLL ref = 250M
assign reg_para[25] = {16'h85, 8'h08}; //Bcount = 8

assign reg_para[26] = {16'h1B5, 8'h09};
assign reg_para[27] = {16'h1BB, 8'h13};
assign reg_para[28] = {16'h1C5, 8'h06};

assign reg_para[29] = {16'h83, 8'h10};
assign reg_para[30] = {16'h84, 8'h01}; //read this Register, only 01 can continue

/*******************STEP 2: DIGITAL DATAPATH*******************/
assign reg_para[31] = {16'h112, 8'h0};
assign reg_para[32] = {16'h110, 8'h80};

/*******************STEP 3: TRANSPORT LAYER*******************/
assign reg_para[33] = {16'h200, 8'h0};
assign reg_para[34] = {16'h201, 8'h0};
assign reg_para[35] = {16'h300, 8'h08};
assign reg_para[36] = {16'h450, 8'h0};
assign reg_para[37] = {16'h451, 8'h0};

assign reg_para[38] = {16'h452, 8'h0};
assign reg_para[39] = {16'h453, 8'h83};
assign reg_para[40] = {16'h454, 8'h0};
assign reg_para[41] = {16'h455, 8'h1F};
assign reg_para[42] = {16'h456, 8'h0};

assign reg_para[43] = {16'h457, 8'h0F};
assign reg_para[44] = {16'h458, 8'h2F};
assign reg_para[45] = {16'h459, 8'h21};
assign reg_para[46] = {16'h45A, 8'h80};
assign reg_para[47] = {16'h45D, 8'h45};

assign reg_para[48] = {16'h46C, 8'hFF};
assign reg_para[49] = {16'h476, 8'h01};
assign reg_para[50] = {16'h47D, 8'hFF};

/*******************STEP 4: PHYSICAL LAYER*******************/
assign reg_para[51] = {16'h2AA, 8'hB7};
assign reg_para[52] = {16'h2AB, 8'h87};
assign reg_para[53] = {16'h2B1, 8'hB7};
assign reg_para[54] = {16'h2B2, 8'h87};
assign reg_para[55] = {16'h2A7, 8'h01};

assign reg_para[56] = {16'h2AE, 8'h01};
assign reg_para[57] = {16'h314, 8'h01};
assign reg_para[58] = {16'h230, 8'h08}; //lane rate is 5G
assign reg_para[59] = {16'h206, 8'h0};
assign reg_para[60] = {16'h206, 8'h1};

assign reg_para[61] = {16'h289, 8'h05}; //lane rate is 5G
assign reg_para[62] = {16'h284, 8'h62};
assign reg_para[63] = {16'h285, 8'hC9};
assign reg_para[64] = {16'h286, 8'h0E};
assign reg_para[65] = {16'h287, 8'h12};

assign reg_para[66] = {16'h28A, 8'h7B};
assign reg_para[67] = {16'h28B, 8'h0};
assign reg_para[68] = {16'h290, 8'h89};
assign reg_para[69] = {16'h294, 8'h24};
assign reg_para[70] = {16'h296, 8'h03};

assign reg_para[71] = {16'h297, 8'h0D};
assign reg_para[72] = {16'h299, 8'h02};
assign reg_para[73] = {16'h29A, 8'h8E};
assign reg_para[74] = {16'h29C, 8'h2A};
assign reg_para[75] = {16'h29F, 8'h78};

assign reg_para[76] = {16'h2A0, 8'h06};
assign reg_para[77] = {16'h280, 8'h01};
assign reg_para[78] = {16'h281, 8'h01}; // Verify that Bit 0 reads back high for SERDES PLL lock
assign reg_para[79] = {16'h268, 8'h62};

/*******************STEP 5: DATA LINK LAYER*******************/
assign reg_para[80] = {16'h301, 8'h01};
assign reg_para[81] = {16'h304, 8'h0};
assign reg_para[82] = {16'h305, 8'h0};
assign reg_para[83] = {16'h306, 8'h0A};
assign reg_para[84] = {16'h307, 8'h0A};

assign reg_para[85] = {16'h308, 8'h01}; //exchange line
assign reg_para[86] = {16'h309, 8'h13};
assign reg_para[87] = {16'h30A, 8'h3C};
assign reg_para[88] = {16'h30B, 8'h35};

assign reg_para[89] = {16'h03A, 8'h01};
assign reg_para[90] = {16'h03A, 8'h81};
assign reg_para[91] = {16'h03A, 8'hC1};
assign reg_para[92] = {16'h300, 8'h01};

assign reg_para[93] = {16'h470, 8'hFF}; //Acknowledge that four consecutive K28.5 characters have been detected on Lane 0 to Lane 3.
assign reg_para[94] = {16'h471, 8'hFF}; //Check for frame sync on all lanes.
assign reg_para[95] = {16'h472, 8'hFF}; //Check for good checksum.
assign reg_para[96] = {16'h473, 8'hFF}; //Check for ILAS.

///////////////////////////// AD9136 config /////////////////////////////


///////////////////////////// HMC7044 config /////////////////////////////
{16bit ADDR, 8bit DATA}
assign reg_para[0] = {16'h0, 8'h0};
assign reg_para[1] = {16'h1, 8'h60};
assign reg_para[2] = {16'h2, 8'h0};
assign reg_para[3] = {16'h3, 8'h36};
assign reg_para[4] = {16'h4, 8'h7f};
assign reg_para[5] = {16'h5, 8'h40};
assign reg_para[6] = {16'h6, 8'h0};
assign reg_para[7] = {16'h7, 8'h0};
assign reg_para[8] = {16'h9, 8'h1};
assign reg_para[9] = {16'ha, 8'h7};

assign reg_para[10] = {16'hb, 8'h7};
assign reg_para[11] = {16'hc, 8'h7};
assign reg_para[12] = {16'hd, 8'h7};
assign reg_para[13] = {16'he, 8'h7};
assign reg_para[14] = {16'h14, 8'he4};
assign reg_para[15] = {16'h15, 8'h0};
assign reg_para[16] = {16'h16, 8'hc};
assign reg_para[17] = {16'h17, 8'h0};
assign reg_para[18] = {16'h18, 8'h0};
assign reg_para[19] = {16'h19, 8'h0};

assign reg_para[20] = {16'h1a, 8'h8};
assign reg_para[21] = {16'h1b, 8'h0};
assign reg_para[22] = {16'h1c, 8'h4};
assign reg_para[23] = {16'h1d, 8'h1};
assign reg_para[24] = {16'h1e, 8'h4};
assign reg_para[25] = {16'h1f, 8'h1};
assign reg_para[26] = {16'h20, 8'h4};
assign reg_para[27] = {16'h21, 8'h4};
assign reg_para[28] = {16'h22, 8'h0};
assign reg_para[29] = {16'h26, 8'h10};

assign reg_para[30] = {16'h27, 8'h0};
assign reg_para[31] = {16'h28, 8'hf};
assign reg_para[32] = {16'h29, 8'h4};
assign reg_para[33] = {16'h2a, 8'h0};
assign reg_para[34] = {16'h31, 8'h1};
assign reg_para[35] = {16'h32, 8'h1};
assign reg_para[36] = {16'h33, 8'h1};
assign reg_para[37] = {16'h34, 8'h0};
assign reg_para[38] = {16'h35, 8'h32}; //clkin is 50M, VCO = 50M*50=2500M, Only use PLL2
assign reg_para[39] = {16'h36, 8'h0};

assign reg_para[40] = {16'h37, 8'hf};
assign reg_para[41] = {16'h38, 8'h18};
assign reg_para[42] = {16'h39, 8'h0};
assign reg_para[43] = {16'h3a, 8'h0};
assign reg_para[44] = {16'h3b, 8'h0};
assign reg_para[45] = {16'h46, 8'h0};
assign reg_para[46] = {16'h47, 8'h0};
assign reg_para[47] = {16'h48, 8'h8};
assign reg_para[48] = {16'h49, 8'h10};
assign reg_para[49] = {16'h50, 8'h2b};

assign reg_para[50] = {16'h51, 8'h32};
assign reg_para[51] = {16'h52, 8'h0};
assign reg_para[52] = {16'h53, 8'h0};
assign reg_para[53] = {16'h54, 8'h3};
assign reg_para[54] = {16'h5a, 8'h7};
assign reg_para[55] = {16'h5b, 8'h6};
assign reg_para[56] = {16'h5c, 8'h0};
assign reg_para[57] = {16'h5d, 8'h1};
assign reg_para[58] = {16'h64, 8'h0};
assign reg_para[59] = {16'h65, 8'h0};

assign reg_para[60] = {16'h70, 8'h8};
assign reg_para[61] = {16'h71, 8'h10};
assign reg_para[62] = {16'h78, 8'h8};
assign reg_para[63] = {16'h79, 8'h9};
assign reg_para[64] = {16'h7a, 8'ha};
assign reg_para[65] = {16'h7b, 8'h1};
assign reg_para[66] = {16'h7c, 8'hc};
assign reg_para[67] = {16'h7d, 8'hd};
assign reg_para[68] = {16'h7e, 8'he};
assign reg_para[69] = {16'h82, 8'hf};

assign reg_para[70] = {16'h83, 8'h0};
assign reg_para[71] = {16'h84, 8'h11};
assign reg_para[72] = {16'h85, 8'h0};
assign reg_para[73] = {16'h86, 8'h0};
assign reg_para[74] = {16'h8c, 8'h2};
assign reg_para[75] = {16'h8d, 8'h3};
assign reg_para[76] = {16'h8e, 8'h4};
assign reg_para[77] = {16'h8f, 8'h5};
assign reg_para[78] = {16'h91, 8'h6};
assign reg_para[79] = {16'h96, 8'h0};

assign reg_para[80] = {16'h97, 8'h0};
assign reg_para[81] = {16'h98, 8'h0};
assign reg_para[82] = {16'h99, 8'h0};
assign reg_para[83] = {16'h9a, 8'h0};
assign reg_para[84] = {16'h9b, 8'haa};
assign reg_para[85] = {16'h9c, 8'haa};
assign reg_para[86] = {16'h9d, 8'haa};
assign reg_para[87] = {16'h9e, 8'haa};
assign reg_para[88] = {16'h9f, 8'h55};
assign reg_para[89] = {16'ha0, 8'h56};

assign reg_para[90] = {16'ha1, 8'h97};
assign reg_para[91] = {16'ha2, 8'h3};
assign reg_para[92] = {16'ha3, 8'h0};
assign reg_para[93] = {16'ha4, 8'h0};
assign reg_para[94] = {16'ha5, 8'h0};
assign reg_para[95] = {16'ha6, 8'h1c};
assign reg_para[96] = {16'ha7, 8'h0};
assign reg_para[97] = {16'ha8, 8'h22};
assign reg_para[98] = {16'ha9, 8'h0};
assign reg_para[99] = {16'hab, 8'h0};

assign reg_para[100] = {16'hac, 8'h20};
assign reg_para[101] = {16'had, 8'h0};
assign reg_para[102] = {16'hae, 8'h8};
assign reg_para[103] = {16'haf, 8'h50};
assign reg_para[104] = {16'hb0, 8'h9};
assign reg_para[105] = {16'hb1, 8'hd};
assign reg_para[106] = {16'hb2, 8'h0};
assign reg_para[107] = {16'hb3, 8'h0};
assign reg_para[108] = {16'hb5, 8'h0};
assign reg_para[109] = {16'hb6, 8'h0};

assign reg_para[110] = {16'hb7, 8'h0};
assign reg_para[111] = {16'hb8, 8'h0};
assign reg_para[112] = {16'hc8, 8'hf3};
assign reg_para[113] = {16'hc9, 8'h80}; //sysref to fpga, f = 2500M / 640
assign reg_para[114] = {16'hca, 8'h2};
assign reg_para[115] = {16'hcb, 8'h0};
assign reg_para[116] = {16'hcc, 8'h0};
assign reg_para[117] = {16'hcd, 8'h0};
assign reg_para[118] = {16'hce, 8'h0};
assign reg_para[119] = {16'hcf, 8'h0};

assign reg_para[120] = {16'hd0, 8'h11};
assign reg_para[121] = {16'hd2, 8'hfd};
assign reg_para[122] = {16'hd3, 8'h0};
assign reg_para[123] = {16'hd4, 8'h3};
assign reg_para[124] = {16'hd5, 8'h0};
assign reg_para[125] = {16'hd6, 8'h0};
assign reg_para[126] = {16'hd7, 8'h0};
assign reg_para[127] = {16'hd8, 8'h0};
assign reg_para[128] = {16'hd9, 8'h0};
assign reg_para[129] = {16'hda, 8'h30};

assign reg_para[130] = {16'hdc, 8'hf3};
assign reg_para[131] = {16'hdd, 8'h5}; //CH2, DAC ref clock = 2500M / 5 = 500M
assign reg_para[132] = {16'hde, 8'h0};
assign reg_para[133] = {16'hdf, 8'h0};
assign reg_para[134] = {16'he0, 8'h0};
assign reg_para[135] = {16'he1, 8'h0};
assign reg_para[136] = {16'he2, 8'h0};
assign reg_para[137] = {16'he3, 8'h0};
assign reg_para[138] = {16'he4, 8'h11};
assign reg_para[139] = {16'he6, 8'hfd};

assign reg_para[140] = {16'he7, 8'h80}; //CH3, DAC sysref = 2500M / 640
assign reg_para[141] = {16'he8, 8'h2};
assign reg_para[142] = {16'he9, 8'h0};
assign reg_para[143] = {16'hea, 8'h0};
assign reg_para[144] = {16'heb, 8'h0};
assign reg_para[145] = {16'hec, 8'h0};
assign reg_para[146] = {16'hed, 8'h0};
assign reg_para[147] = {16'hee, 8'h30};
assign reg_para[148] = {16'hf0, 8'hf3};
assign reg_para[149] = {16'hf1, 8'h6};

assign reg_para[150] = {16'hf2, 8'h0};
assign reg_para[151] = {16'hf3, 8'h0};
assign reg_para[152] = {16'hf4, 8'h0};
assign reg_para[153] = {16'hf5, 8'h0};
assign reg_para[154] = {16'hf6, 8'h0};
assign reg_para[155] = {16'hf7, 8'h0};
assign reg_para[156] = {16'hf8, 8'h11};
assign reg_para[157] = {16'hfa, 8'hf5};
assign reg_para[158] = {16'hfb, 8'h0};
assign reg_para[159] = {16'hfc, 8'h3};

assign reg_para[160] = {16'hfd, 8'h0};
assign reg_para[161] = {16'hfe, 8'h0};
assign reg_para[162] = {16'hff, 8'h0};
assign reg_para[163] = {16'h100, 8'h0};
assign reg_para[164] = {16'h101, 8'h0};
assign reg_para[165] = {16'h102, 8'h30};
assign reg_para[166] = {16'h104, 8'hf3};
assign reg_para[167] = {16'h105, 8'h6};
assign reg_para[168] = {16'h106, 8'h0};
assign reg_para[169] = {16'h107, 8'h0};

assign reg_para[170] = {16'h108, 8'h0};
assign reg_para[171] = {16'h109, 8'h0};
assign reg_para[172] = {16'h10a, 8'h0};
assign reg_para[173] = {16'h10b, 8'h0};
assign reg_para[174] = {16'h10c, 8'h11};
assign reg_para[175] = {16'h10e, 8'hfd};
assign reg_para[176] = {16'h10f, 8'h0};
assign reg_para[177] = {16'h110, 8'h3};
assign reg_para[178] = {16'h111, 8'h0};
assign reg_para[179] = {16'h112, 8'h0};

assign reg_para[180] = {16'h113, 8'h0};
assign reg_para[181] = {16'h114, 8'h0};
assign reg_para[182] = {16'h115, 8'h0};
assign reg_para[183] = {16'h116, 8'h30};
assign reg_para[184] = {16'h118, 8'hf3};
assign reg_para[185] = {16'h119, 8'h6};
assign reg_para[186] = {16'h11a, 8'h0};
assign reg_para[187] = {16'h11b, 8'h0};
assign reg_para[188] = {16'h11c, 8'h0};
assign reg_para[189] = {16'h11d, 8'h0};

assign reg_para[190] = {16'h11e, 8'h0};
assign reg_para[191] = {16'h11f, 8'h0};
assign reg_para[192] = {16'h120, 8'h11};
assign reg_para[193] = {16'h122, 8'hfd};
assign reg_para[194] = {16'h123, 8'h0};
assign reg_para[195] = {16'h124, 8'h3};
assign reg_para[196] = {16'h125, 8'h0};
assign reg_para[197] = {16'h126, 8'h0};
assign reg_para[198] = {16'h127, 8'h0};
assign reg_para[199] = {16'h128, 8'h0};

assign reg_para[200] = {16'h129, 8'h0};
assign reg_para[201] = {16'h12a, 8'h30};
assign reg_para[202] = {16'h12c, 8'hf3};
assign reg_para[203] = {16'h12d, 8'ha}; //CH10, gtx clk0 = 2500M / 10 = 250M
assign reg_para[204] = {16'h12e, 8'h0};
assign reg_para[205] = {16'h12f, 8'h0};
assign reg_para[206] = {16'h130, 8'h0};
assign reg_para[207] = {16'h131, 8'h0};
assign reg_para[208] = {16'h132, 8'h0};
assign reg_para[209] = {16'h133, 8'h0};

assign reg_para[210] = {16'h134, 8'h11};
assign reg_para[211] = {16'h136, 8'hf3};
assign reg_para[212] = {16'h137, 8'h80}; //CH11 50 divide, cc0
assign reg_para[213] = {16'h138, 8'h2};
assign reg_para[214] = {16'h139, 8'h0};
assign reg_para[215] = {16'h13a, 8'h0};
assign reg_para[216] = {16'h13b, 8'h0};
assign reg_para[217] = {16'h13c, 8'h0};
assign reg_para[218] = {16'h13d, 8'h0};
assign reg_para[219] = {16'h13e, 8'h30};

assign reg_para[220] = {16'h140, 8'hf3};
assign reg_para[221] = {16'h141, 8'ha}; //CH12 20 divide, gtx clk1 = 2500M / 10 = 250M
assign reg_para[222] = {16'h142, 8'h0};
assign reg_para[223] = {16'h143, 8'h0};
assign reg_para[224] = {16'h144, 8'h0};
assign reg_para[225] = {16'h145, 8'h0};
assign reg_para[226] = {16'h146, 8'h0};
assign reg_para[227] = {16'h147, 8'h0};
assign reg_para[228] = {16'h148, 8'h11};
assign reg_para[229] = {16'h14a, 8'hf3};

assign reg_para[230] = {16'h14b, 8'h80}; //CH13 640 divide, cc2
assign reg_para[231] = {16'h14c, 8'h2};
assign reg_para[232] = {16'h14d, 8'h9};
assign reg_para[233] = {16'h14e, 8'h0};
assign reg_para[234] = {16'h14f, 8'h0};
assign reg_para[235] = {16'h150, 8'h0};
assign reg_para[236] = {16'h151, 8'h0};
assign reg_para[237] = {16'h152, 8'h30};

assign reg_para[238] = {16'h1, 8'h62};
assign reg_para[239] = {16'h1, 8'h60};

///////////////////////////// HMC7044 config /////////////////////////////

///////////////////////////// JESD204 AXI config /////////////////////////////

write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x008, 0x00000001);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x00C, 0x00000001);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x010, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x014, 0x00000003);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x018, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x020, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x024, 0x0000001F);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x028, 0x000000FF);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x02C, 0x00000001);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x80C, 0x00000000);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x810, 0x000F0F01);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x814, 0x00010101);
usleep(1);
write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x818, 0x00000000);

///////////////////////////// JESD204 AXI config /////////////////////////////

When FPGA keeps sending K28.5, it will also find sync going in and out, I tried to change lanerate(10G, 3G), but it also didn't work. Thank you!