ZC706 with AD9136-FMC-EBZ Code Group Sync going in and out

I am trying to get the ZC706 with AD9136-FMC-EBZ running with the following settings:

DAC GOAL:
====================================
1 GSPS per channel (2 GSPS total)

AD9516 CLOCK SYNTHESIS SETTINGS
====================================
Root Oscillator: 250.0 MHz
DAC CLK+/CLK- (REFCLK): 125.0 MHz
DAC SYSREF: 15.625 MHz

FPGA SYSREF: 15.625 MHz
FPGA GTX REFCLK: 125.0 MHz

I am using the Analog Devices Reference design in non-OS mode (Linux is not supported yet), so it's utilizing the ADI blocks in the FPGA firmware. I have verified that I am getting the correct TXUSRCLK from the Zynq's GTX.

My problem is that I am getting a continual SYNC pulse from the DAC. In analyzing the registers, it appears that the "CODEGRPSYNC" flags (register 0x470) are going in and out for some lanes. I could not identify any obvious problem from other registers, except that it's not receiving any of the JESD204B parameters over the line (probably hasn't got far enough into the decoding process).

Any suggestions on troubleshooting this? 

I have created a register dump printout for every single register that is being configured (including hardware and ADI AXI IP). Hopefully someone can spot a problem with this configuration:

REGISTER DUMP
====================================
AD9516 CLKGEN: Addr=0x0000. Data=0x99
AD9516 CLKGEN: Addr=0x0003. Data=0x41
AD9516 CLKGEN: Addr=0x0004. Data=0x01
AD9516 CLKGEN: Addr=0x0010. Data=0x7d
AD9516 CLKGEN: Addr=0x0011. Data=0x01
AD9516 CLKGEN: Addr=0x0012. Data=0x00
AD9516 CLKGEN: Addr=0x0013. Data=0x00
AD9516 CLKGEN: Addr=0x0014. Data=0x03
AD9516 CLKGEN: Addr=0x0015. Data=0x00
AD9516 CLKGEN: Addr=0x0016. Data=0x06
AD9516 CLKGEN: Addr=0x0017. Data=0x00
AD9516 CLKGEN: Addr=0x0018. Data=0x01
AD9516 CLKGEN: Addr=0x0019. Data=0x00
AD9516 CLKGEN: Addr=0x001a. Data=0x00
AD9516 CLKGEN: Addr=0x001b. Data=0x00
AD9516 CLKGEN: Addr=0x001c. Data=0x00
AD9516 CLKGEN: Addr=0x001d. Data=0x00
AD9516 CLKGEN: Addr=0x001e. Data=0x00
AD9516 CLKGEN: Addr=0x001f. Data=0x0e
AD9516 CLKGEN: Addr=0x00a0. Data=0x01
AD9516 CLKGEN: Addr=0x00a1. Data=0x00
AD9516 CLKGEN: Addr=0x00a2. Data=0x00
AD9516 CLKGEN: Addr=0x00a3. Data=0x01
AD9516 CLKGEN: Addr=0x00a4. Data=0x00
AD9516 CLKGEN: Addr=0x00a5. Data=0x00
AD9516 CLKGEN: Addr=0x00a6. Data=0x01
AD9516 CLKGEN: Addr=0x00a7. Data=0x00
AD9516 CLKGEN: Addr=0x00a8. Data=0x00
AD9516 CLKGEN: Addr=0x00a9. Data=0x01
AD9516 CLKGEN: Addr=0x00aa. Data=0x00
AD9516 CLKGEN: Addr=0x00ab. Data=0x00
AD9516 CLKGEN: Addr=0x00f0. Data=0x0a
AD9516 CLKGEN: Addr=0x00f1. Data=0x08
AD9516 CLKGEN: Addr=0x00f2. Data=0x0a
AD9516 CLKGEN: Addr=0x00f3. Data=0x0a
AD9516 CLKGEN: Addr=0x00f4. Data=0x0a
AD9516 CLKGEN: Addr=0x00f5. Data=0x0a
AD9516 CLKGEN: Addr=0x0140. Data=0x42
AD9516 CLKGEN: Addr=0x0141. Data=0x42
AD9516 CLKGEN: Addr=0x0142. Data=0x43
AD9516 CLKGEN: Addr=0x0143. Data=0x42
AD9516 CLKGEN: Addr=0x0190. Data=0x00
AD9516 CLKGEN: Addr=0x0191. Data=0x80
AD9516 CLKGEN: Addr=0x0192. Data=0x01
AD9516 CLKGEN: Addr=0x0193. Data=0xbb
AD9516 CLKGEN: Addr=0x0194. Data=0x00
AD9516 CLKGEN: Addr=0x0195. Data=0x00
AD9516 CLKGEN: Addr=0x0196. Data=0x33
AD9516 CLKGEN: Addr=0x0197. Data=0x00
AD9516 CLKGEN: Addr=0x0198. Data=0x00
AD9516 CLKGEN: Addr=0x0199. Data=0x00
AD9516 CLKGEN: Addr=0x019a. Data=0x00
AD9516 CLKGEN: Addr=0x019b. Data=0x11
AD9516 CLKGEN: Addr=0x019c. Data=0x00
AD9516 CLKGEN: Addr=0x019d. Data=0x00
AD9516 CLKGEN: Addr=0x019e. Data=0x00
AD9516 CLKGEN: Addr=0x019f. Data=0x00
AD9516 CLKGEN: Addr=0x01a0. Data=0x00
AD9516 CLKGEN: Addr=0x01a1. Data=0x30
AD9516 CLKGEN: Addr=0x01a2. Data=0x00
AD9516 CLKGEN: Addr=0x01e0. Data=0x00
AD9516 CLKGEN: Addr=0x01e1. Data=0x00
AD9516 CLKGEN: Addr=0x0230. Data=0x00
AD9516 CLKGEN: Addr=0x0232. Data=0x00

AD9136 DAC: Addr=0x0000. Data=0x18
AD9136 DAC: Addr=0x0003. Data=0x04
AD9136 DAC: Addr=0x0004. Data=0x44
AD9136 DAC: Addr=0x0005. Data=0x91
AD9136 DAC: Addr=0x0006. Data=0x68
AD9136 DAC: Addr=0x0008. Data=0x03
AD9136 DAC: Addr=0x000a. Data=0x00
AD9136 DAC: Addr=0x0011. Data=0x28
AD9136 DAC: Addr=0x0012. Data=0x00
AD9136 DAC: Addr=0x0013. Data=0x20
AD9136 DAC: Addr=0x0014. Data=0x88
AD9136 DAC: Addr=0x001f. Data=0x00
AD9136 DAC: Addr=0x0020. Data=0x00
AD9136 DAC: Addr=0x0021. Data=0x00
AD9136 DAC: Addr=0x0022. Data=0x00
AD9136 DAC: Addr=0x0023. Data=0x14
AD9136 DAC: Addr=0x0024. Data=0x00
AD9136 DAC: Addr=0x0025. Data=0x00
AD9136 DAC: Addr=0x0026. Data=0x00
AD9136 DAC: Addr=0x0030. Data=0x00
AD9136 DAC: Addr=0x0034. Data=0x00
AD9136 DAC: Addr=0x0038. Data=0xd8
AD9136 DAC: Addr=0x0039. Data=0x81
AD9136 DAC: Addr=0x003a. Data=0x81
AD9136 DAC: Addr=0x003b. Data=0x0d
AD9136 DAC: Addr=0x003c. Data=0x00
AD9136 DAC: Addr=0x003d. Data=0x00
AD9136 DAC: Addr=0x0040. Data=0x00
AD9136 DAC: Addr=0x0041. Data=0x00
AD9136 DAC: Addr=0x0044. Data=0x00
AD9136 DAC: Addr=0x0045. Data=0x00
AD9136 DAC: Addr=0x0080. Data=0x00
AD9136 DAC: Addr=0x0081. Data=0x00
AD9136 DAC: Addr=0x0082. Data=0x00
AD9136 DAC: Addr=0x0083. Data=0x10
AD9136 DAC: Addr=0x0084. Data=0x22
AD9136 DAC: Addr=0x0085. Data=0x08
AD9136 DAC: Addr=0x0087. Data=0x62
AD9136 DAC: Addr=0x0088. Data=0xc9
AD9136 DAC: Addr=0x0089. Data=0x0e
AD9136 DAC: Addr=0x008a. Data=0x12
AD9136 DAC: Addr=0x008b. Data=0x02
AD9136 DAC: Addr=0x008c. Data=0x01
AD9136 DAC: Addr=0x008d. Data=0x7b
AD9136 DAC: Addr=0x00e2. Data=0x00
AD9136 DAC: Addr=0x00e7. Data=0x30
AD9136 DAC: Addr=0x00e8. Data=0x0f
AD9136 DAC: Addr=0x00e9. Data=0x00
AD9136 DAC: Addr=0x00ed. Data=0xa6
AD9136 DAC: Addr=0x0110. Data=0x00
AD9136 DAC: Addr=0x0111. Data=0x00
AD9136 DAC: Addr=0x0112. Data=0x00
AD9136 DAC: Addr=0x011f. Data=0x83
AD9136 DAC: Addr=0x0121. Data=0x0f
AD9136 DAC: Addr=0x0122. Data=0x00
AD9136 DAC: Addr=0x0123. Data=0xff
AD9136 DAC: Addr=0x0124. Data=0xff
AD9136 DAC: Addr=0x012d. Data=0x8b
AD9136 DAC: Addr=0x012f. Data=0x20
AD9136 DAC: Addr=0x0132. Data=0x00
AD9136 DAC: Addr=0x0133. Data=0x00
AD9136 DAC: Addr=0x0134. Data=0x00
AD9136 DAC: Addr=0x0135. Data=0x00
AD9136 DAC: Addr=0x0136. Data=0x00
AD9136 DAC: Addr=0x0137. Data=0x00
AD9136 DAC: Addr=0x013a. Data=0x00
AD9136 DAC: Addr=0x013c. Data=0xea
AD9136 DAC: Addr=0x013d. Data=0x0a
AD9136 DAC: Addr=0x0140. Data=0x04
AD9136 DAC: Addr=0x0141. Data=0x00
AD9136 DAC: Addr=0x0142. Data=0x09
AD9136 DAC: Addr=0x0143. Data=0x00
AD9136 DAC: Addr=0x0146. Data=0x01
AD9136 DAC: Addr=0x0147. Data=0x4a
AD9136 DAC: Addr=0x014b. Data=0xc5
AD9136 DAC: Addr=0x014c. Data=0x00
AD9136 DAC: Addr=0x01b0. Data=0x00
AD9136 DAC: Addr=0x01b5. Data=0x89
AD9136 DAC: Addr=0x01b9. Data=0x24
AD9136 DAC: Addr=0x01bb. Data=0x13
AD9136 DAC: Addr=0x01bc. Data=0x0d
AD9136 DAC: Addr=0x01be. Data=0x02
AD9136 DAC: Addr=0x01bf. Data=0x8e
AD9136 DAC: Addr=0x01c0. Data=0x2a
AD9136 DAC: Addr=0x01c1. Data=0x2a
AD9136 DAC: Addr=0x01c4. Data=0x7e
AD9136 DAC: Addr=0x01c5. Data=0x06
AD9136 DAC: Addr=0x0200. Data=0x00
AD9136 DAC: Addr=0x0201. Data=0x00
AD9136 DAC: Addr=0x0203. Data=0x00
AD9136 DAC: Addr=0x0206. Data=0x01
AD9136 DAC: Addr=0x0230. Data=0x08
AD9136 DAC: Addr=0x0232. Data=0xff
AD9136 DAC: Addr=0x0268. Data=0x62
AD9136 DAC: Addr=0x0280. Data=0x01
AD9136 DAC: Addr=0x0281. Data=0x0b
AD9136 DAC: Addr=0x0284. Data=0x62
AD9136 DAC: Addr=0x0285. Data=0xc9
AD9136 DAC: Addr=0x0286. Data=0x0e
AD9136 DAC: Addr=0x0287. Data=0x12
AD9136 DAC: Addr=0x0289. Data=0x05
AD9136 DAC: Addr=0x028a. Data=0x7b
AD9136 DAC: Addr=0x028b. Data=0x00
AD9136 DAC: Addr=0x0290. Data=0x89
AD9136 DAC: Addr=0x0294. Data=0x24
AD9136 DAC: Addr=0x0296. Data=0x03
AD9136 DAC: Addr=0x0297. Data=0x0d
AD9136 DAC: Addr=0x0299. Data=0x02
AD9136 DAC: Addr=0x029a. Data=0x8e
AD9136 DAC: Addr=0x029c. Data=0x2a
AD9136 DAC: Addr=0x029f. Data=0x78
AD9136 DAC: Addr=0x02a0. Data=0x06
AD9136 DAC: Addr=0x02a4. Data=0xff
AD9136 DAC: Addr=0x02a5. Data=0x00
AD9136 DAC: Addr=0x02a7. Data=0x01
AD9136 DAC: Addr=0x02aa. Data=0xb7
AD9136 DAC: Addr=0x02ab. Data=0x87
AD9136 DAC: Addr=0x02ae. Data=0x01
AD9136 DAC: Addr=0x02b1. Data=0xb7
AD9136 DAC: Addr=0x02b2. Data=0x87
AD9136 DAC: Addr=0x0300. Data=0x01
AD9136 DAC: Addr=0x0301. Data=0x01
AD9136 DAC: Addr=0x0302. Data=0x00
AD9136 DAC: Addr=0x0303. Data=0x00
AD9136 DAC: Addr=0x0304. Data=0x00
AD9136 DAC: Addr=0x0305. Data=0x00
AD9136 DAC: Addr=0x0306. Data=0x0a
AD9136 DAC: Addr=0x0307. Data=0x0a
AD9136 DAC: Addr=0x0308. Data=0x08
AD9136 DAC: Addr=0x0309. Data=0x1a
AD9136 DAC: Addr=0x030a. Data=0x2c
AD9136 DAC: Addr=0x030b. Data=0x3e
AD9136 DAC: Addr=0x030c. Data=0x00
AD9136 DAC: Addr=0x030d. Data=0x00
AD9136 DAC: Addr=0x0312. Data=0x00
AD9136 DAC: Addr=0x0314. Data=0x01
AD9136 DAC: Addr=0x0315. Data=0x00
AD9136 DAC: Addr=0x0316. Data=0x00
AD9136 DAC: Addr=0x0317. Data=0x00
AD9136 DAC: Addr=0x0318. Data=0x00
AD9136 DAC: Addr=0x0319. Data=0x00
AD9136 DAC: Addr=0x031a. Data=0x00
AD9136 DAC: Addr=0x031b. Data=0x00
AD9136 DAC: Addr=0x031c. Data=0x00
AD9136 DAC: Addr=0x031d. Data=0xff
AD9136 DAC: Addr=0x032c. Data=0x00
AD9136 DAC: Addr=0x032d. Data=0x00
AD9136 DAC: Addr=0x032e. Data=0x00
AD9136 DAC: Addr=0x032f. Data=0x00
AD9136 DAC: Addr=0x0333. Data=0x01
AD9136 DAC: Addr=0x0334. Data=0x0f
AD9136 DAC: Addr=0x0400. Data=0x00
AD9136 DAC: Addr=0x0401. Data=0x00
AD9136 DAC: Addr=0x0402. Data=0x00
AD9136 DAC: Addr=0x0403. Data=0x00
AD9136 DAC: Addr=0x0404. Data=0x00
AD9136 DAC: Addr=0x0405. Data=0x00
AD9136 DAC: Addr=0x0406. Data=0x00
AD9136 DAC: Addr=0x0407. Data=0x00
AD9136 DAC: Addr=0x0408. Data=0x00
AD9136 DAC: Addr=0x0409. Data=0x00
AD9136 DAC: Addr=0x040a. Data=0x00
AD9136 DAC: Addr=0x040b. Data=0x00
AD9136 DAC: Addr=0x040c. Data=0x00
AD9136 DAC: Addr=0x040d. Data=0x00
AD9136 DAC: Addr=0x040e. Data=0x00
AD9136 DAC: Addr=0x0412. Data=0x00
AD9136 DAC: Addr=0x0415. Data=0x00
AD9136 DAC: Addr=0x0416. Data=0x00
AD9136 DAC: Addr=0x041a. Data=0x00
AD9136 DAC: Addr=0x041d. Data=0x00
AD9136 DAC: Addr=0x041e. Data=0x00
AD9136 DAC: Addr=0x0422. Data=0x00
AD9136 DAC: Addr=0x0425. Data=0x00
AD9136 DAC: Addr=0x0426. Data=0x00
AD9136 DAC: Addr=0x042a. Data=0x00
AD9136 DAC: Addr=0x042d. Data=0x00
AD9136 DAC: Addr=0x042e. Data=0x00
AD9136 DAC: Addr=0x0432. Data=0x00
AD9136 DAC: Addr=0x0435. Data=0x00
AD9136 DAC: Addr=0x0436. Data=0x00
AD9136 DAC: Addr=0x043a. Data=0x00
AD9136 DAC: Addr=0x043d. Data=0x00
AD9136 DAC: Addr=0x043e. Data=0x00
AD9136 DAC: Addr=0x0442. Data=0x00
AD9136 DAC: Addr=0x0445. Data=0x00
AD9136 DAC: Addr=0x0446. Data=0x00
AD9136 DAC: Addr=0x0450. Data=0xab
AD9136 DAC: Addr=0x0451. Data=0x02
AD9136 DAC: Addr=0x0452. Data=0x00
AD9136 DAC: Addr=0x0453. Data=0x83
AD9136 DAC: Addr=0x0454. Data=0x00
AD9136 DAC: Addr=0x0455. Data=0x1f
AD9136 DAC: Addr=0x0456. Data=0x00
AD9136 DAC: Addr=0x0457. Data=0x0f
AD9136 DAC: Addr=0x0458. Data=0x2f
AD9136 DAC: Addr=0x0459. Data=0x21
AD9136 DAC: Addr=0x045a. Data=0x80
AD9136 DAC: Addr=0x045b. Data=0x00
AD9136 DAC: Addr=0x045c. Data=0x00
AD9136 DAC: Addr=0x045d. Data=0x33
AD9136 DAC: Addr=0x046b. Data=0x00
AD9136 DAC: Addr=0x046b. Data=0x00
AD9136 DAC: Addr=0x046c. Data=0xff
AD9136 DAC: Addr=0x046d. Data=0x00
AD9136 DAC: Addr=0x046d. Data=0x00
AD9136 DAC: Addr=0x046e. Data=0x00
AD9136 DAC: Addr=0x046e. Data=0x00
AD9136 DAC: Addr=0x046f. Data=0x00
AD9136 DAC: Addr=0x046f. Data=0x00
AD9136 DAC: Addr=0x0470. Data=0x04
AD9136 DAC: Addr=0x0471. Data=0xff
AD9136 DAC: Addr=0x0472. Data=0x00
AD9136 DAC: Addr=0x0473. Data=0x00
AD9136 DAC: Addr=0x0476. Data=0x01
AD9136 DAC: Addr=0x0477. Data=0x00
AD9136 DAC: Addr=0x0478. Data=0x01
AD9136 DAC: Addr=0x047a. Data=0x01
AD9136 DAC: Addr=0x047a. Data=0x01
AD9136 DAC: Addr=0x047b. Data=0x08
AD9136 DAC: Addr=0x047c. Data=0xff
AD9136 DAC: Addr=0x047d. Data=0xff
AD9136 DAC: Addr=0x047e. Data=0x00
AD9136 DAC: Addr=0x0520. Data=0x1c
AD9136 DAC: Addr=0x0521. Data=0x00
AD9136 DAC: Addr=0x0522. Data=0x00

JESD204_TX: Addr=0x0000. Data=0x00010361
JESD204_TX: Addr=0x0004. Data=0x00000000
JESD204_TX: Addr=0x0008. Data=0x00000000
JESD204_TX: Addr=0x000c. Data=0x32303454
JESD204_TX: Addr=0x0010. Data=0x00000008
JESD204_TX: Addr=0x0014. Data=0x00000002
JESD204_TX: Addr=0x0018. Data=0x00000101
JESD204_TX: Addr=0x0080. Data=0x00000000
JESD204_TX: Addr=0x0084. Data=0x00000000
JESD204_TX: Addr=0x0088. Data=0x00000000
JESD204_TX: Addr=0x00c0. Data=0x00000000
JESD204_TX: Addr=0x00c4. Data=0x00000000
JESD204_TX: Addr=0x00c8. Data=0x00050004
JESD204_TX: Addr=0x0100. Data=0x00000000
JESD204_TX: Addr=0x0104. Data=0x00000000
JESD204_TX: Addr=0x0108. Data=0x00000003
JESD204_TX: Addr=0x0200. Data=0x00000000
JESD204_TX: Addr=0x0210. Data=0x0000001f
JESD204_TX: Addr=0x0214. Data=0x00000002
JESD204_TX: Addr=0x0218. Data=0x00000000
JESD204_TX: Addr=0x0240. Data=0x00000000
JESD204_TX: Addr=0x0244. Data=0x00000003
JESD204_TX: Addr=0x0248. Data=0x00000000
JESD204_TX: Addr=0x0280. Data=0x00000001
JESD204_TX: Addr=0x0310. Data=0x02ab0000
JESD204_TX: Addr=0x0314. Data=0x00018800
JESD204_TX: Addr=0x0318. Data=0x22301002
JESD204_TX: Addr=0x031c. Data=0x3a000080
JESD204_TX: Addr=0x0330. Data=0x02ab0000
JESD204_TX: Addr=0x0334. Data=0x00018801
JESD204_TX: Addr=0x0338. Data=0x22301002
JESD204_TX: Addr=0x033c. Data=0x3b000080
JESD204_TX: Addr=0x0350. Data=0x02ab0000
JESD204_TX: Addr=0x0354. Data=0x00018802
JESD204_TX: Addr=0x0358. Data=0x22301002
JESD204_TX: Addr=0x035c. Data=0x3c000080
JESD204_TX: Addr=0x0370. Data=0x02ab0000
JESD204_TX: Addr=0x0374. Data=0x00018803
JESD204_TX: Addr=0x0378. Data=0x22301002
JESD204_TX: Addr=0x037c. Data=0x3d000080
JESD204_TX: Addr=0x0390. Data=0x02ab0000
JESD204_TX: Addr=0x0394. Data=0x00018804
JESD204_TX: Addr=0x0398. Data=0x22301002
JESD204_TX: Addr=0x039c. Data=0x3e000080
JESD204_TX: Addr=0x03b0. Data=0x02ab0000
JESD204_TX: Addr=0x03b4. Data=0x00018805
JESD204_TX: Addr=0x03b8. Data=0x22301002
JESD204_TX: Addr=0x03bc. Data=0x3f000080
JESD204_TX: Addr=0x03d0. Data=0x02ab0000
JESD204_TX: Addr=0x03d4. Data=0x00018806
JESD204_TX: Addr=0x03d8. Data=0x22301002
JESD204_TX: Addr=0x03dc. Data=0x40000080
JESD204_TX: Addr=0x03f0. Data=0x02ab0000
JESD204_TX: Addr=0x03f4. Data=0x00018807
JESD204_TX: Addr=0x03f8. Data=0x22301002
JESD204_TX: Addr=0x03fc. Data=0x41000080

JESD204_TPL: Addr=0x0000. Data=0x00090162
JESD204_TPL: Addr=0x0004. Data=0x00000000
JESD204_TPL: Addr=0x0008. Data=0x00000000
JESD204_TPL: Addr=0x000c. Data=0x00000001
JESD204_TPL: Addr=0x0010. Data=0x00000000
JESD204_TPL: Addr=0x001c. Data=0x00000000
JESD204_TPL: Addr=0x0040. Data=0x00000003
JESD204_TPL: Addr=0x0044. Data=0x00000000
JESD204_TPL: Addr=0x0048. Data=0x00000000
JESD204_TPL: Addr=0x004c. Data=0x00000001
JESD204_TPL: Addr=0x0050. Data=0x00000000
JESD204_TPL: Addr=0x0054. Data=0x00050005
JESD204_TPL: Addr=0x0058. Data=0x00000008
JESD204_TPL: Addr=0x005c. Data=0x00000001
JESD204_TPL: Addr=0x0060. Data=0x00000000
JESD204_TPL: Addr=0x0070. Data=0x00000000
JESD204_TPL: Addr=0x0074. Data=0x00020000
JESD204_TPL: Addr=0x0078. Data=0x00000000
JESD204_TPL: Addr=0x007c. Data=0x00000000
JESD204_TPL: Addr=0x0088. Data=0x00000000
JESD204_TPL: Addr=0x00a0. Data=0x00000002
JESD204_TPL: Addr=0x00b8. Data=0x00000000
JESD204_TPL: Addr=0x00bc. Data=0x00000000
JESD204_TPL: Addr=0x0200. Data=0x00000000
JESD204_TPL: Addr=0x0204. Data=0x00000001
JESD204_TPL: Addr=0x0240. Data=0x01020802
JESD204_TPL: Addr=0x0244. Data=0x00001010
JESD204_TPL: Addr=0x0400. Data=0x00000000
JESD204_TPL: Addr=0x0404. Data=0x00000000
JESD204_TPL: Addr=0x0408. Data=0x00000000
JESD204_TPL: Addr=0x040c. Data=0x00000000
JESD204_TPL: Addr=0x0410. Data=0x00000000
JESD204_TPL: Addr=0x0414. Data=0x00000000
JESD204_TPL: Addr=0x0418. Data=0x00000000
JESD204_TPL: Addr=0x041c. Data=0x00000000
JESD204_TPL: Addr=0x0420. Data=0x01001010
JESD204_TPL: Addr=0x0424. Data=0x00010001
JESD204_TPL: Addr=0x0428. Data=0x00000000
JESD204_TPL: Addr=0x0440. Data=0x00000000
JESD204_TPL: Addr=0x0444. Data=0x00000000
JESD204_TPL: Addr=0x0448. Data=0x00000000
JESD204_TPL: Addr=0x044c. Data=0x00000000
JESD204_TPL: Addr=0x0450. Data=0x00000000
JESD204_TPL: Addr=0x0454. Data=0x00000000
JESD204_TPL: Addr=0x0458. Data=0x00000000
JESD204_TPL: Addr=0x045c. Data=0x00000000
JESD204_TPL: Addr=0x0460. Data=0x01001010
JESD204_TPL: Addr=0x0464. Data=0x00010001
JESD204_TPL: Addr=0x0468. Data=0x00000000

Parents
  • 0
    •  Analog Employees 
    on Aug 31, 2020 6:31 AM

    Hi

    it looks there is a device tree available for the 9136 here: 

    https://github.com/analogdevicesinc/linux/blob/master/arch/arm/boot/dts/zynq-zc706-adv7511-ad9136-fmc-ebz.dts

    How did you build the hdl. what parameters did you used, what operation mode did you select for the JESD ? 

    Thank you, 

    Laszlo

  • I did see the device tree, but it's currently "not supported" and I couldn't figure out how to get it to build (I was given some instructions to try here: https://ez.analog.com/linux-software-drivers/f/q-a/167077/zc706-and-ad9136-how-to-include-reference-design-dtsi-file, but I couldn't figure it out). Thus, I went with bare metal CPU. For HDL, I built the analog devices "dac_fmc_ebz" reference design for the zc706 target. I configured the "config.tcl" to use JESD mode 11 set for device AD9136, single link mode, which should give these parameters:

    M = 2

    L = 8

    S = 2

    F = 1

    HD = 1

    N = 16

    Np = 16

  • Hello, I also find a similar problem. The sync signal kept going in and out. I checked the clock, channel, etc., and found no errors. I let FPGA send K28.5 all the time, and found that sync is also going in and out in the same way. May I ask what may be the cause of this problem? Thank you

  • 0
    •  Analog Employees 
    on Apr 26, 2021 9:32 AM in reply to fengyi

    Please can you open a thread with the setup you have ? 

    Thanks, 

    Laszlo

  • This is the phenomenon when sending normal data and K28.5

  • Hello, this is a PCB designed by myself. The parameters are:

    DAC CLK: 500MHz

    DAC sysref: 3.90625MHz

    FPGA sysref: 3.90625MHz

    FPGA gtxclk: 250MHz

    And I use HMC7044 to generate the clock

    ///////////////////////////// AD9136 config /////////////////////////////
    /*******************STEP 1: START UP THE DAC*******************/
    {16bit ADDR, 8bit DATA}
    assign reg_para[0] = {16'h0, 8'hA5};
    assign reg_para[1] = {16'h0, 8'h24};
    assign reg_para[2] = {16'h11, 8'h28};
    assign reg_para[3] = {16'h80, 8'h0};
    assign reg_para[4] = {16'h81, 8'h0};
    
    assign reg_para[5] = {16'h12D, 8'h8B};
    assign reg_para[6] = {16'h146, 8'h01};
    assign reg_para[7] = {16'h2A4, 8'hFF};
    assign reg_para[8] = {16'h232, 8'hFF};
    assign reg_para[9] = {16'h333, 8'h01};
    
    assign reg_para[10] = {16'h87, 8'h62};
    assign reg_para[11] = {16'h88, 8'hC9};
    assign reg_para[12] = {16'h89, 8'h0E};
    assign reg_para[13] = {16'h8A, 8'h12};
    assign reg_para[14] = {16'h8D, 8'h7B};
    
    assign reg_para[15] = {16'h1B0, 8'h0};
    assign reg_para[16] = {16'h1B9, 8'h24};
    assign reg_para[17] = {16'h1BC, 8'h0D};
    assign reg_para[18] = {16'h1BE, 8'h02};
    assign reg_para[19] = {16'h1BF, 8'h8E};
    
    assign reg_para[20] = {16'h1C0, 8'h2A};
    assign reg_para[21] = {16'h1C1, 8'h2A};
    assign reg_para[22] = {16'h1C4, 8'h7E};
    
    assign reg_para[23] = {16'h8B, 8'h02}; //fDAC = 1G
    assign reg_para[24] = {16'h8C, 8'h02}; //DAC PLL ref = 250M
    assign reg_para[25] = {16'h85, 8'h08}; //Bcount = 8
    
    assign reg_para[26] = {16'h1B5, 8'h09};
    assign reg_para[27] = {16'h1BB, 8'h13};
    assign reg_para[28] = {16'h1C5, 8'h06};
    
    assign reg_para[29] = {16'h83, 8'h10};
    assign reg_para[30] = {16'h84, 8'h01}; //read this Register, only 01 can continue
    
    /*******************STEP 2: DIGITAL DATAPATH*******************/
    assign reg_para[31] = {16'h112, 8'h0};
    assign reg_para[32] = {16'h110, 8'h80};
    
    /*******************STEP 3: TRANSPORT LAYER*******************/
    assign reg_para[33] = {16'h200, 8'h0};
    assign reg_para[34] = {16'h201, 8'h0};
    assign reg_para[35] = {16'h300, 8'h08};
    assign reg_para[36] = {16'h450, 8'h0};
    assign reg_para[37] = {16'h451, 8'h0};
    
    assign reg_para[38] = {16'h452, 8'h0};
    assign reg_para[39] = {16'h453, 8'h83};
    assign reg_para[40] = {16'h454, 8'h0};
    assign reg_para[41] = {16'h455, 8'h1F};
    assign reg_para[42] = {16'h456, 8'h0};
    
    assign reg_para[43] = {16'h457, 8'h0F};
    assign reg_para[44] = {16'h458, 8'h2F};
    assign reg_para[45] = {16'h459, 8'h21};
    assign reg_para[46] = {16'h45A, 8'h80};
    assign reg_para[47] = {16'h45D, 8'h45};
    
    assign reg_para[48] = {16'h46C, 8'hFF};
    assign reg_para[49] = {16'h476, 8'h01};
    assign reg_para[50] = {16'h47D, 8'hFF};
    
    /*******************STEP 4: PHYSICAL LAYER*******************/
    assign reg_para[51] = {16'h2AA, 8'hB7};
    assign reg_para[52] = {16'h2AB, 8'h87};
    assign reg_para[53] = {16'h2B1, 8'hB7};
    assign reg_para[54] = {16'h2B2, 8'h87};
    assign reg_para[55] = {16'h2A7, 8'h01};
    
    assign reg_para[56] = {16'h2AE, 8'h01};
    assign reg_para[57] = {16'h314, 8'h01};
    assign reg_para[58] = {16'h230, 8'h08}; //lane rate is 5G
    assign reg_para[59] = {16'h206, 8'h0};
    assign reg_para[60] = {16'h206, 8'h1};
    
    assign reg_para[61] = {16'h289, 8'h05}; //lane rate is 5G
    assign reg_para[62] = {16'h284, 8'h62};
    assign reg_para[63] = {16'h285, 8'hC9};
    assign reg_para[64] = {16'h286, 8'h0E};
    assign reg_para[65] = {16'h287, 8'h12};
    
    assign reg_para[66] = {16'h28A, 8'h7B};
    assign reg_para[67] = {16'h28B, 8'h0};
    assign reg_para[68] = {16'h290, 8'h89};
    assign reg_para[69] = {16'h294, 8'h24};
    assign reg_para[70] = {16'h296, 8'h03};
    
    assign reg_para[71] = {16'h297, 8'h0D};
    assign reg_para[72] = {16'h299, 8'h02};
    assign reg_para[73] = {16'h29A, 8'h8E};
    assign reg_para[74] = {16'h29C, 8'h2A};
    assign reg_para[75] = {16'h29F, 8'h78};
    
    assign reg_para[76] = {16'h2A0, 8'h06};
    assign reg_para[77] = {16'h280, 8'h01};
    assign reg_para[78] = {16'h281, 8'h01}; // Verify that Bit 0 reads back high for SERDES PLL lock
    assign reg_para[79] = {16'h268, 8'h62};
    
    /*******************STEP 5: DATA LINK LAYER*******************/
    assign reg_para[80] = {16'h301, 8'h01};
    assign reg_para[81] = {16'h304, 8'h0};
    assign reg_para[82] = {16'h305, 8'h0};
    assign reg_para[83] = {16'h306, 8'h0A};
    assign reg_para[84] = {16'h307, 8'h0A};
    
    assign reg_para[85] = {16'h308, 8'h01}; //exchange line
    assign reg_para[86] = {16'h309, 8'h13};
    assign reg_para[87] = {16'h30A, 8'h3C};
    assign reg_para[88] = {16'h30B, 8'h35};
    
    assign reg_para[89] = {16'h03A, 8'h01};
    assign reg_para[90] = {16'h03A, 8'h81};
    assign reg_para[91] = {16'h03A, 8'hC1};
    assign reg_para[92] = {16'h300, 8'h01};
    
    assign reg_para[93] = {16'h470, 8'hFF}; //Acknowledge that four consecutive K28.5 characters have been detected on Lane 0 to Lane 3.
    assign reg_para[94] = {16'h471, 8'hFF}; //Check for frame sync on all lanes.
    assign reg_para[95] = {16'h472, 8'hFF}; //Check for good checksum.
    assign reg_para[96] = {16'h473, 8'hFF}; //Check for ILAS.
    
    ///////////////////////////// AD9136 config /////////////////////////////
    
    
    ///////////////////////////// HMC7044 config /////////////////////////////
    {16bit ADDR, 8bit DATA}
    assign reg_para[0] = {16'h0, 8'h0};
    assign reg_para[1] = {16'h1, 8'h60};
    assign reg_para[2] = {16'h2, 8'h0};
    assign reg_para[3] = {16'h3, 8'h36};
    assign reg_para[4] = {16'h4, 8'h7f};
    assign reg_para[5] = {16'h5, 8'h40};
    assign reg_para[6] = {16'h6, 8'h0};
    assign reg_para[7] = {16'h7, 8'h0};
    assign reg_para[8] = {16'h9, 8'h1};
    assign reg_para[9] = {16'ha, 8'h7};
    
    assign reg_para[10] = {16'hb, 8'h7};
    assign reg_para[11] = {16'hc, 8'h7};
    assign reg_para[12] = {16'hd, 8'h7};
    assign reg_para[13] = {16'he, 8'h7};
    assign reg_para[14] = {16'h14, 8'he4};
    assign reg_para[15] = {16'h15, 8'h0};
    assign reg_para[16] = {16'h16, 8'hc};
    assign reg_para[17] = {16'h17, 8'h0};
    assign reg_para[18] = {16'h18, 8'h0};
    assign reg_para[19] = {16'h19, 8'h0};
    
    assign reg_para[20] = {16'h1a, 8'h8};
    assign reg_para[21] = {16'h1b, 8'h0};
    assign reg_para[22] = {16'h1c, 8'h4};
    assign reg_para[23] = {16'h1d, 8'h1};
    assign reg_para[24] = {16'h1e, 8'h4};
    assign reg_para[25] = {16'h1f, 8'h1};
    assign reg_para[26] = {16'h20, 8'h4};
    assign reg_para[27] = {16'h21, 8'h4};
    assign reg_para[28] = {16'h22, 8'h0};
    assign reg_para[29] = {16'h26, 8'h10};
    
    assign reg_para[30] = {16'h27, 8'h0};
    assign reg_para[31] = {16'h28, 8'hf};
    assign reg_para[32] = {16'h29, 8'h4};
    assign reg_para[33] = {16'h2a, 8'h0};
    assign reg_para[34] = {16'h31, 8'h1};
    assign reg_para[35] = {16'h32, 8'h1};
    assign reg_para[36] = {16'h33, 8'h1};
    assign reg_para[37] = {16'h34, 8'h0};
    assign reg_para[38] = {16'h35, 8'h32}; //clkin is 50M, VCO = 50M*50=2500M, Only use PLL2
    assign reg_para[39] = {16'h36, 8'h0};
    
    assign reg_para[40] = {16'h37, 8'hf};
    assign reg_para[41] = {16'h38, 8'h18};
    assign reg_para[42] = {16'h39, 8'h0};
    assign reg_para[43] = {16'h3a, 8'h0};
    assign reg_para[44] = {16'h3b, 8'h0};
    assign reg_para[45] = {16'h46, 8'h0};
    assign reg_para[46] = {16'h47, 8'h0};
    assign reg_para[47] = {16'h48, 8'h8};
    assign reg_para[48] = {16'h49, 8'h10};
    assign reg_para[49] = {16'h50, 8'h2b};
    
    assign reg_para[50] = {16'h51, 8'h32};
    assign reg_para[51] = {16'h52, 8'h0};
    assign reg_para[52] = {16'h53, 8'h0};
    assign reg_para[53] = {16'h54, 8'h3};
    assign reg_para[54] = {16'h5a, 8'h7};
    assign reg_para[55] = {16'h5b, 8'h6};
    assign reg_para[56] = {16'h5c, 8'h0};
    assign reg_para[57] = {16'h5d, 8'h1};
    assign reg_para[58] = {16'h64, 8'h0};
    assign reg_para[59] = {16'h65, 8'h0};
    
    assign reg_para[60] = {16'h70, 8'h8};
    assign reg_para[61] = {16'h71, 8'h10};
    assign reg_para[62] = {16'h78, 8'h8};
    assign reg_para[63] = {16'h79, 8'h9};
    assign reg_para[64] = {16'h7a, 8'ha};
    assign reg_para[65] = {16'h7b, 8'h1};
    assign reg_para[66] = {16'h7c, 8'hc};
    assign reg_para[67] = {16'h7d, 8'hd};
    assign reg_para[68] = {16'h7e, 8'he};
    assign reg_para[69] = {16'h82, 8'hf};
    
    assign reg_para[70] = {16'h83, 8'h0};
    assign reg_para[71] = {16'h84, 8'h11};
    assign reg_para[72] = {16'h85, 8'h0};
    assign reg_para[73] = {16'h86, 8'h0};
    assign reg_para[74] = {16'h8c, 8'h2};
    assign reg_para[75] = {16'h8d, 8'h3};
    assign reg_para[76] = {16'h8e, 8'h4};
    assign reg_para[77] = {16'h8f, 8'h5};
    assign reg_para[78] = {16'h91, 8'h6};
    assign reg_para[79] = {16'h96, 8'h0};
    
    assign reg_para[80] = {16'h97, 8'h0};
    assign reg_para[81] = {16'h98, 8'h0};
    assign reg_para[82] = {16'h99, 8'h0};
    assign reg_para[83] = {16'h9a, 8'h0};
    assign reg_para[84] = {16'h9b, 8'haa};
    assign reg_para[85] = {16'h9c, 8'haa};
    assign reg_para[86] = {16'h9d, 8'haa};
    assign reg_para[87] = {16'h9e, 8'haa};
    assign reg_para[88] = {16'h9f, 8'h55};
    assign reg_para[89] = {16'ha0, 8'h56};
    
    assign reg_para[90] = {16'ha1, 8'h97};
    assign reg_para[91] = {16'ha2, 8'h3};
    assign reg_para[92] = {16'ha3, 8'h0};
    assign reg_para[93] = {16'ha4, 8'h0};
    assign reg_para[94] = {16'ha5, 8'h0};
    assign reg_para[95] = {16'ha6, 8'h1c};
    assign reg_para[96] = {16'ha7, 8'h0};
    assign reg_para[97] = {16'ha8, 8'h22};
    assign reg_para[98] = {16'ha9, 8'h0};
    assign reg_para[99] = {16'hab, 8'h0};
    
    assign reg_para[100] = {16'hac, 8'h20};
    assign reg_para[101] = {16'had, 8'h0};
    assign reg_para[102] = {16'hae, 8'h8};
    assign reg_para[103] = {16'haf, 8'h50};
    assign reg_para[104] = {16'hb0, 8'h9};
    assign reg_para[105] = {16'hb1, 8'hd};
    assign reg_para[106] = {16'hb2, 8'h0};
    assign reg_para[107] = {16'hb3, 8'h0};
    assign reg_para[108] = {16'hb5, 8'h0};
    assign reg_para[109] = {16'hb6, 8'h0};
    
    assign reg_para[110] = {16'hb7, 8'h0};
    assign reg_para[111] = {16'hb8, 8'h0};
    assign reg_para[112] = {16'hc8, 8'hf3};
    assign reg_para[113] = {16'hc9, 8'h80}; //sysref to fpga, f = 2500M / 640
    assign reg_para[114] = {16'hca, 8'h2};
    assign reg_para[115] = {16'hcb, 8'h0};
    assign reg_para[116] = {16'hcc, 8'h0};
    assign reg_para[117] = {16'hcd, 8'h0};
    assign reg_para[118] = {16'hce, 8'h0};
    assign reg_para[119] = {16'hcf, 8'h0};
    
    assign reg_para[120] = {16'hd0, 8'h11};
    assign reg_para[121] = {16'hd2, 8'hfd};
    assign reg_para[122] = {16'hd3, 8'h0};
    assign reg_para[123] = {16'hd4, 8'h3};
    assign reg_para[124] = {16'hd5, 8'h0};
    assign reg_para[125] = {16'hd6, 8'h0};
    assign reg_para[126] = {16'hd7, 8'h0};
    assign reg_para[127] = {16'hd8, 8'h0};
    assign reg_para[128] = {16'hd9, 8'h0};
    assign reg_para[129] = {16'hda, 8'h30};
    
    assign reg_para[130] = {16'hdc, 8'hf3};
    assign reg_para[131] = {16'hdd, 8'h5}; //CH2, DAC ref clock = 2500M / 5 = 500M
    assign reg_para[132] = {16'hde, 8'h0};
    assign reg_para[133] = {16'hdf, 8'h0};
    assign reg_para[134] = {16'he0, 8'h0};
    assign reg_para[135] = {16'he1, 8'h0};
    assign reg_para[136] = {16'he2, 8'h0};
    assign reg_para[137] = {16'he3, 8'h0};
    assign reg_para[138] = {16'he4, 8'h11};
    assign reg_para[139] = {16'he6, 8'hfd};
    
    assign reg_para[140] = {16'he7, 8'h80}; //CH3, DAC sysref = 2500M / 640
    assign reg_para[141] = {16'he8, 8'h2};
    assign reg_para[142] = {16'he9, 8'h0};
    assign reg_para[143] = {16'hea, 8'h0};
    assign reg_para[144] = {16'heb, 8'h0};
    assign reg_para[145] = {16'hec, 8'h0};
    assign reg_para[146] = {16'hed, 8'h0};
    assign reg_para[147] = {16'hee, 8'h30};
    assign reg_para[148] = {16'hf0, 8'hf3};
    assign reg_para[149] = {16'hf1, 8'h6};
    
    assign reg_para[150] = {16'hf2, 8'h0};
    assign reg_para[151] = {16'hf3, 8'h0};
    assign reg_para[152] = {16'hf4, 8'h0};
    assign reg_para[153] = {16'hf5, 8'h0};
    assign reg_para[154] = {16'hf6, 8'h0};
    assign reg_para[155] = {16'hf7, 8'h0};
    assign reg_para[156] = {16'hf8, 8'h11};
    assign reg_para[157] = {16'hfa, 8'hf5};
    assign reg_para[158] = {16'hfb, 8'h0};
    assign reg_para[159] = {16'hfc, 8'h3};
    
    assign reg_para[160] = {16'hfd, 8'h0};
    assign reg_para[161] = {16'hfe, 8'h0};
    assign reg_para[162] = {16'hff, 8'h0};
    assign reg_para[163] = {16'h100, 8'h0};
    assign reg_para[164] = {16'h101, 8'h0};
    assign reg_para[165] = {16'h102, 8'h30};
    assign reg_para[166] = {16'h104, 8'hf3};
    assign reg_para[167] = {16'h105, 8'h6};
    assign reg_para[168] = {16'h106, 8'h0};
    assign reg_para[169] = {16'h107, 8'h0};
    
    assign reg_para[170] = {16'h108, 8'h0};
    assign reg_para[171] = {16'h109, 8'h0};
    assign reg_para[172] = {16'h10a, 8'h0};
    assign reg_para[173] = {16'h10b, 8'h0};
    assign reg_para[174] = {16'h10c, 8'h11};
    assign reg_para[175] = {16'h10e, 8'hfd};
    assign reg_para[176] = {16'h10f, 8'h0};
    assign reg_para[177] = {16'h110, 8'h3};
    assign reg_para[178] = {16'h111, 8'h0};
    assign reg_para[179] = {16'h112, 8'h0};
    
    assign reg_para[180] = {16'h113, 8'h0};
    assign reg_para[181] = {16'h114, 8'h0};
    assign reg_para[182] = {16'h115, 8'h0};
    assign reg_para[183] = {16'h116, 8'h30};
    assign reg_para[184] = {16'h118, 8'hf3};
    assign reg_para[185] = {16'h119, 8'h6};
    assign reg_para[186] = {16'h11a, 8'h0};
    assign reg_para[187] = {16'h11b, 8'h0};
    assign reg_para[188] = {16'h11c, 8'h0};
    assign reg_para[189] = {16'h11d, 8'h0};
    
    assign reg_para[190] = {16'h11e, 8'h0};
    assign reg_para[191] = {16'h11f, 8'h0};
    assign reg_para[192] = {16'h120, 8'h11};
    assign reg_para[193] = {16'h122, 8'hfd};
    assign reg_para[194] = {16'h123, 8'h0};
    assign reg_para[195] = {16'h124, 8'h3};
    assign reg_para[196] = {16'h125, 8'h0};
    assign reg_para[197] = {16'h126, 8'h0};
    assign reg_para[198] = {16'h127, 8'h0};
    assign reg_para[199] = {16'h128, 8'h0};
    
    assign reg_para[200] = {16'h129, 8'h0};
    assign reg_para[201] = {16'h12a, 8'h30};
    assign reg_para[202] = {16'h12c, 8'hf3};
    assign reg_para[203] = {16'h12d, 8'ha}; //CH10, gtx clk0 = 2500M / 10 = 250M
    assign reg_para[204] = {16'h12e, 8'h0};
    assign reg_para[205] = {16'h12f, 8'h0};
    assign reg_para[206] = {16'h130, 8'h0};
    assign reg_para[207] = {16'h131, 8'h0};
    assign reg_para[208] = {16'h132, 8'h0};
    assign reg_para[209] = {16'h133, 8'h0};
    
    assign reg_para[210] = {16'h134, 8'h11};
    assign reg_para[211] = {16'h136, 8'hf3};
    assign reg_para[212] = {16'h137, 8'h80}; //CH11 50 divide, cc0
    assign reg_para[213] = {16'h138, 8'h2};
    assign reg_para[214] = {16'h139, 8'h0};
    assign reg_para[215] = {16'h13a, 8'h0};
    assign reg_para[216] = {16'h13b, 8'h0};
    assign reg_para[217] = {16'h13c, 8'h0};
    assign reg_para[218] = {16'h13d, 8'h0};
    assign reg_para[219] = {16'h13e, 8'h30};
    
    assign reg_para[220] = {16'h140, 8'hf3};
    assign reg_para[221] = {16'h141, 8'ha}; //CH12 20 divide, gtx clk1 = 2500M / 10 = 250M
    assign reg_para[222] = {16'h142, 8'h0};
    assign reg_para[223] = {16'h143, 8'h0};
    assign reg_para[224] = {16'h144, 8'h0};
    assign reg_para[225] = {16'h145, 8'h0};
    assign reg_para[226] = {16'h146, 8'h0};
    assign reg_para[227] = {16'h147, 8'h0};
    assign reg_para[228] = {16'h148, 8'h11};
    assign reg_para[229] = {16'h14a, 8'hf3};
    
    assign reg_para[230] = {16'h14b, 8'h80}; //CH13 640 divide, cc2
    assign reg_para[231] = {16'h14c, 8'h2};
    assign reg_para[232] = {16'h14d, 8'h9};
    assign reg_para[233] = {16'h14e, 8'h0};
    assign reg_para[234] = {16'h14f, 8'h0};
    assign reg_para[235] = {16'h150, 8'h0};
    assign reg_para[236] = {16'h151, 8'h0};
    assign reg_para[237] = {16'h152, 8'h30};
    
    assign reg_para[238] = {16'h1, 8'h62};
    assign reg_para[239] = {16'h1, 8'h60};
    
    ///////////////////////////// HMC7044 config /////////////////////////////
    
    ///////////////////////////// JESD204 AXI config /////////////////////////////
    
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x008, 0x00000001);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x00C, 0x00000001);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x010, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x014, 0x00000003);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x018, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x020, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x024, 0x0000001F);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x028, 0x000000FF);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x02C, 0x00000001);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x80C, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x810, 0x000F0F01);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x814, 0x00010101);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x818, 0x00000000);
    
    ///////////////////////////// JESD204 AXI config /////////////////////////////
    

    When FPGA keeps sending K28.5, it will also find sync going in and out, I tried to change lanerate(10G, 3G), but it also didn't work. Thank you!

Reply
  • Hello, this is a PCB designed by myself. The parameters are:

    DAC CLK: 500MHz

    DAC sysref: 3.90625MHz

    FPGA sysref: 3.90625MHz

    FPGA gtxclk: 250MHz

    And I use HMC7044 to generate the clock

    ///////////////////////////// AD9136 config /////////////////////////////
    /*******************STEP 1: START UP THE DAC*******************/
    {16bit ADDR, 8bit DATA}
    assign reg_para[0] = {16'h0, 8'hA5};
    assign reg_para[1] = {16'h0, 8'h24};
    assign reg_para[2] = {16'h11, 8'h28};
    assign reg_para[3] = {16'h80, 8'h0};
    assign reg_para[4] = {16'h81, 8'h0};
    
    assign reg_para[5] = {16'h12D, 8'h8B};
    assign reg_para[6] = {16'h146, 8'h01};
    assign reg_para[7] = {16'h2A4, 8'hFF};
    assign reg_para[8] = {16'h232, 8'hFF};
    assign reg_para[9] = {16'h333, 8'h01};
    
    assign reg_para[10] = {16'h87, 8'h62};
    assign reg_para[11] = {16'h88, 8'hC9};
    assign reg_para[12] = {16'h89, 8'h0E};
    assign reg_para[13] = {16'h8A, 8'h12};
    assign reg_para[14] = {16'h8D, 8'h7B};
    
    assign reg_para[15] = {16'h1B0, 8'h0};
    assign reg_para[16] = {16'h1B9, 8'h24};
    assign reg_para[17] = {16'h1BC, 8'h0D};
    assign reg_para[18] = {16'h1BE, 8'h02};
    assign reg_para[19] = {16'h1BF, 8'h8E};
    
    assign reg_para[20] = {16'h1C0, 8'h2A};
    assign reg_para[21] = {16'h1C1, 8'h2A};
    assign reg_para[22] = {16'h1C4, 8'h7E};
    
    assign reg_para[23] = {16'h8B, 8'h02}; //fDAC = 1G
    assign reg_para[24] = {16'h8C, 8'h02}; //DAC PLL ref = 250M
    assign reg_para[25] = {16'h85, 8'h08}; //Bcount = 8
    
    assign reg_para[26] = {16'h1B5, 8'h09};
    assign reg_para[27] = {16'h1BB, 8'h13};
    assign reg_para[28] = {16'h1C5, 8'h06};
    
    assign reg_para[29] = {16'h83, 8'h10};
    assign reg_para[30] = {16'h84, 8'h01}; //read this Register, only 01 can continue
    
    /*******************STEP 2: DIGITAL DATAPATH*******************/
    assign reg_para[31] = {16'h112, 8'h0};
    assign reg_para[32] = {16'h110, 8'h80};
    
    /*******************STEP 3: TRANSPORT LAYER*******************/
    assign reg_para[33] = {16'h200, 8'h0};
    assign reg_para[34] = {16'h201, 8'h0};
    assign reg_para[35] = {16'h300, 8'h08};
    assign reg_para[36] = {16'h450, 8'h0};
    assign reg_para[37] = {16'h451, 8'h0};
    
    assign reg_para[38] = {16'h452, 8'h0};
    assign reg_para[39] = {16'h453, 8'h83};
    assign reg_para[40] = {16'h454, 8'h0};
    assign reg_para[41] = {16'h455, 8'h1F};
    assign reg_para[42] = {16'h456, 8'h0};
    
    assign reg_para[43] = {16'h457, 8'h0F};
    assign reg_para[44] = {16'h458, 8'h2F};
    assign reg_para[45] = {16'h459, 8'h21};
    assign reg_para[46] = {16'h45A, 8'h80};
    assign reg_para[47] = {16'h45D, 8'h45};
    
    assign reg_para[48] = {16'h46C, 8'hFF};
    assign reg_para[49] = {16'h476, 8'h01};
    assign reg_para[50] = {16'h47D, 8'hFF};
    
    /*******************STEP 4: PHYSICAL LAYER*******************/
    assign reg_para[51] = {16'h2AA, 8'hB7};
    assign reg_para[52] = {16'h2AB, 8'h87};
    assign reg_para[53] = {16'h2B1, 8'hB7};
    assign reg_para[54] = {16'h2B2, 8'h87};
    assign reg_para[55] = {16'h2A7, 8'h01};
    
    assign reg_para[56] = {16'h2AE, 8'h01};
    assign reg_para[57] = {16'h314, 8'h01};
    assign reg_para[58] = {16'h230, 8'h08}; //lane rate is 5G
    assign reg_para[59] = {16'h206, 8'h0};
    assign reg_para[60] = {16'h206, 8'h1};
    
    assign reg_para[61] = {16'h289, 8'h05}; //lane rate is 5G
    assign reg_para[62] = {16'h284, 8'h62};
    assign reg_para[63] = {16'h285, 8'hC9};
    assign reg_para[64] = {16'h286, 8'h0E};
    assign reg_para[65] = {16'h287, 8'h12};
    
    assign reg_para[66] = {16'h28A, 8'h7B};
    assign reg_para[67] = {16'h28B, 8'h0};
    assign reg_para[68] = {16'h290, 8'h89};
    assign reg_para[69] = {16'h294, 8'h24};
    assign reg_para[70] = {16'h296, 8'h03};
    
    assign reg_para[71] = {16'h297, 8'h0D};
    assign reg_para[72] = {16'h299, 8'h02};
    assign reg_para[73] = {16'h29A, 8'h8E};
    assign reg_para[74] = {16'h29C, 8'h2A};
    assign reg_para[75] = {16'h29F, 8'h78};
    
    assign reg_para[76] = {16'h2A0, 8'h06};
    assign reg_para[77] = {16'h280, 8'h01};
    assign reg_para[78] = {16'h281, 8'h01}; // Verify that Bit 0 reads back high for SERDES PLL lock
    assign reg_para[79] = {16'h268, 8'h62};
    
    /*******************STEP 5: DATA LINK LAYER*******************/
    assign reg_para[80] = {16'h301, 8'h01};
    assign reg_para[81] = {16'h304, 8'h0};
    assign reg_para[82] = {16'h305, 8'h0};
    assign reg_para[83] = {16'h306, 8'h0A};
    assign reg_para[84] = {16'h307, 8'h0A};
    
    assign reg_para[85] = {16'h308, 8'h01}; //exchange line
    assign reg_para[86] = {16'h309, 8'h13};
    assign reg_para[87] = {16'h30A, 8'h3C};
    assign reg_para[88] = {16'h30B, 8'h35};
    
    assign reg_para[89] = {16'h03A, 8'h01};
    assign reg_para[90] = {16'h03A, 8'h81};
    assign reg_para[91] = {16'h03A, 8'hC1};
    assign reg_para[92] = {16'h300, 8'h01};
    
    assign reg_para[93] = {16'h470, 8'hFF}; //Acknowledge that four consecutive K28.5 characters have been detected on Lane 0 to Lane 3.
    assign reg_para[94] = {16'h471, 8'hFF}; //Check for frame sync on all lanes.
    assign reg_para[95] = {16'h472, 8'hFF}; //Check for good checksum.
    assign reg_para[96] = {16'h473, 8'hFF}; //Check for ILAS.
    
    ///////////////////////////// AD9136 config /////////////////////////////
    
    
    ///////////////////////////// HMC7044 config /////////////////////////////
    {16bit ADDR, 8bit DATA}
    assign reg_para[0] = {16'h0, 8'h0};
    assign reg_para[1] = {16'h1, 8'h60};
    assign reg_para[2] = {16'h2, 8'h0};
    assign reg_para[3] = {16'h3, 8'h36};
    assign reg_para[4] = {16'h4, 8'h7f};
    assign reg_para[5] = {16'h5, 8'h40};
    assign reg_para[6] = {16'h6, 8'h0};
    assign reg_para[7] = {16'h7, 8'h0};
    assign reg_para[8] = {16'h9, 8'h1};
    assign reg_para[9] = {16'ha, 8'h7};
    
    assign reg_para[10] = {16'hb, 8'h7};
    assign reg_para[11] = {16'hc, 8'h7};
    assign reg_para[12] = {16'hd, 8'h7};
    assign reg_para[13] = {16'he, 8'h7};
    assign reg_para[14] = {16'h14, 8'he4};
    assign reg_para[15] = {16'h15, 8'h0};
    assign reg_para[16] = {16'h16, 8'hc};
    assign reg_para[17] = {16'h17, 8'h0};
    assign reg_para[18] = {16'h18, 8'h0};
    assign reg_para[19] = {16'h19, 8'h0};
    
    assign reg_para[20] = {16'h1a, 8'h8};
    assign reg_para[21] = {16'h1b, 8'h0};
    assign reg_para[22] = {16'h1c, 8'h4};
    assign reg_para[23] = {16'h1d, 8'h1};
    assign reg_para[24] = {16'h1e, 8'h4};
    assign reg_para[25] = {16'h1f, 8'h1};
    assign reg_para[26] = {16'h20, 8'h4};
    assign reg_para[27] = {16'h21, 8'h4};
    assign reg_para[28] = {16'h22, 8'h0};
    assign reg_para[29] = {16'h26, 8'h10};
    
    assign reg_para[30] = {16'h27, 8'h0};
    assign reg_para[31] = {16'h28, 8'hf};
    assign reg_para[32] = {16'h29, 8'h4};
    assign reg_para[33] = {16'h2a, 8'h0};
    assign reg_para[34] = {16'h31, 8'h1};
    assign reg_para[35] = {16'h32, 8'h1};
    assign reg_para[36] = {16'h33, 8'h1};
    assign reg_para[37] = {16'h34, 8'h0};
    assign reg_para[38] = {16'h35, 8'h32}; //clkin is 50M, VCO = 50M*50=2500M, Only use PLL2
    assign reg_para[39] = {16'h36, 8'h0};
    
    assign reg_para[40] = {16'h37, 8'hf};
    assign reg_para[41] = {16'h38, 8'h18};
    assign reg_para[42] = {16'h39, 8'h0};
    assign reg_para[43] = {16'h3a, 8'h0};
    assign reg_para[44] = {16'h3b, 8'h0};
    assign reg_para[45] = {16'h46, 8'h0};
    assign reg_para[46] = {16'h47, 8'h0};
    assign reg_para[47] = {16'h48, 8'h8};
    assign reg_para[48] = {16'h49, 8'h10};
    assign reg_para[49] = {16'h50, 8'h2b};
    
    assign reg_para[50] = {16'h51, 8'h32};
    assign reg_para[51] = {16'h52, 8'h0};
    assign reg_para[52] = {16'h53, 8'h0};
    assign reg_para[53] = {16'h54, 8'h3};
    assign reg_para[54] = {16'h5a, 8'h7};
    assign reg_para[55] = {16'h5b, 8'h6};
    assign reg_para[56] = {16'h5c, 8'h0};
    assign reg_para[57] = {16'h5d, 8'h1};
    assign reg_para[58] = {16'h64, 8'h0};
    assign reg_para[59] = {16'h65, 8'h0};
    
    assign reg_para[60] = {16'h70, 8'h8};
    assign reg_para[61] = {16'h71, 8'h10};
    assign reg_para[62] = {16'h78, 8'h8};
    assign reg_para[63] = {16'h79, 8'h9};
    assign reg_para[64] = {16'h7a, 8'ha};
    assign reg_para[65] = {16'h7b, 8'h1};
    assign reg_para[66] = {16'h7c, 8'hc};
    assign reg_para[67] = {16'h7d, 8'hd};
    assign reg_para[68] = {16'h7e, 8'he};
    assign reg_para[69] = {16'h82, 8'hf};
    
    assign reg_para[70] = {16'h83, 8'h0};
    assign reg_para[71] = {16'h84, 8'h11};
    assign reg_para[72] = {16'h85, 8'h0};
    assign reg_para[73] = {16'h86, 8'h0};
    assign reg_para[74] = {16'h8c, 8'h2};
    assign reg_para[75] = {16'h8d, 8'h3};
    assign reg_para[76] = {16'h8e, 8'h4};
    assign reg_para[77] = {16'h8f, 8'h5};
    assign reg_para[78] = {16'h91, 8'h6};
    assign reg_para[79] = {16'h96, 8'h0};
    
    assign reg_para[80] = {16'h97, 8'h0};
    assign reg_para[81] = {16'h98, 8'h0};
    assign reg_para[82] = {16'h99, 8'h0};
    assign reg_para[83] = {16'h9a, 8'h0};
    assign reg_para[84] = {16'h9b, 8'haa};
    assign reg_para[85] = {16'h9c, 8'haa};
    assign reg_para[86] = {16'h9d, 8'haa};
    assign reg_para[87] = {16'h9e, 8'haa};
    assign reg_para[88] = {16'h9f, 8'h55};
    assign reg_para[89] = {16'ha0, 8'h56};
    
    assign reg_para[90] = {16'ha1, 8'h97};
    assign reg_para[91] = {16'ha2, 8'h3};
    assign reg_para[92] = {16'ha3, 8'h0};
    assign reg_para[93] = {16'ha4, 8'h0};
    assign reg_para[94] = {16'ha5, 8'h0};
    assign reg_para[95] = {16'ha6, 8'h1c};
    assign reg_para[96] = {16'ha7, 8'h0};
    assign reg_para[97] = {16'ha8, 8'h22};
    assign reg_para[98] = {16'ha9, 8'h0};
    assign reg_para[99] = {16'hab, 8'h0};
    
    assign reg_para[100] = {16'hac, 8'h20};
    assign reg_para[101] = {16'had, 8'h0};
    assign reg_para[102] = {16'hae, 8'h8};
    assign reg_para[103] = {16'haf, 8'h50};
    assign reg_para[104] = {16'hb0, 8'h9};
    assign reg_para[105] = {16'hb1, 8'hd};
    assign reg_para[106] = {16'hb2, 8'h0};
    assign reg_para[107] = {16'hb3, 8'h0};
    assign reg_para[108] = {16'hb5, 8'h0};
    assign reg_para[109] = {16'hb6, 8'h0};
    
    assign reg_para[110] = {16'hb7, 8'h0};
    assign reg_para[111] = {16'hb8, 8'h0};
    assign reg_para[112] = {16'hc8, 8'hf3};
    assign reg_para[113] = {16'hc9, 8'h80}; //sysref to fpga, f = 2500M / 640
    assign reg_para[114] = {16'hca, 8'h2};
    assign reg_para[115] = {16'hcb, 8'h0};
    assign reg_para[116] = {16'hcc, 8'h0};
    assign reg_para[117] = {16'hcd, 8'h0};
    assign reg_para[118] = {16'hce, 8'h0};
    assign reg_para[119] = {16'hcf, 8'h0};
    
    assign reg_para[120] = {16'hd0, 8'h11};
    assign reg_para[121] = {16'hd2, 8'hfd};
    assign reg_para[122] = {16'hd3, 8'h0};
    assign reg_para[123] = {16'hd4, 8'h3};
    assign reg_para[124] = {16'hd5, 8'h0};
    assign reg_para[125] = {16'hd6, 8'h0};
    assign reg_para[126] = {16'hd7, 8'h0};
    assign reg_para[127] = {16'hd8, 8'h0};
    assign reg_para[128] = {16'hd9, 8'h0};
    assign reg_para[129] = {16'hda, 8'h30};
    
    assign reg_para[130] = {16'hdc, 8'hf3};
    assign reg_para[131] = {16'hdd, 8'h5}; //CH2, DAC ref clock = 2500M / 5 = 500M
    assign reg_para[132] = {16'hde, 8'h0};
    assign reg_para[133] = {16'hdf, 8'h0};
    assign reg_para[134] = {16'he0, 8'h0};
    assign reg_para[135] = {16'he1, 8'h0};
    assign reg_para[136] = {16'he2, 8'h0};
    assign reg_para[137] = {16'he3, 8'h0};
    assign reg_para[138] = {16'he4, 8'h11};
    assign reg_para[139] = {16'he6, 8'hfd};
    
    assign reg_para[140] = {16'he7, 8'h80}; //CH3, DAC sysref = 2500M / 640
    assign reg_para[141] = {16'he8, 8'h2};
    assign reg_para[142] = {16'he9, 8'h0};
    assign reg_para[143] = {16'hea, 8'h0};
    assign reg_para[144] = {16'heb, 8'h0};
    assign reg_para[145] = {16'hec, 8'h0};
    assign reg_para[146] = {16'hed, 8'h0};
    assign reg_para[147] = {16'hee, 8'h30};
    assign reg_para[148] = {16'hf0, 8'hf3};
    assign reg_para[149] = {16'hf1, 8'h6};
    
    assign reg_para[150] = {16'hf2, 8'h0};
    assign reg_para[151] = {16'hf3, 8'h0};
    assign reg_para[152] = {16'hf4, 8'h0};
    assign reg_para[153] = {16'hf5, 8'h0};
    assign reg_para[154] = {16'hf6, 8'h0};
    assign reg_para[155] = {16'hf7, 8'h0};
    assign reg_para[156] = {16'hf8, 8'h11};
    assign reg_para[157] = {16'hfa, 8'hf5};
    assign reg_para[158] = {16'hfb, 8'h0};
    assign reg_para[159] = {16'hfc, 8'h3};
    
    assign reg_para[160] = {16'hfd, 8'h0};
    assign reg_para[161] = {16'hfe, 8'h0};
    assign reg_para[162] = {16'hff, 8'h0};
    assign reg_para[163] = {16'h100, 8'h0};
    assign reg_para[164] = {16'h101, 8'h0};
    assign reg_para[165] = {16'h102, 8'h30};
    assign reg_para[166] = {16'h104, 8'hf3};
    assign reg_para[167] = {16'h105, 8'h6};
    assign reg_para[168] = {16'h106, 8'h0};
    assign reg_para[169] = {16'h107, 8'h0};
    
    assign reg_para[170] = {16'h108, 8'h0};
    assign reg_para[171] = {16'h109, 8'h0};
    assign reg_para[172] = {16'h10a, 8'h0};
    assign reg_para[173] = {16'h10b, 8'h0};
    assign reg_para[174] = {16'h10c, 8'h11};
    assign reg_para[175] = {16'h10e, 8'hfd};
    assign reg_para[176] = {16'h10f, 8'h0};
    assign reg_para[177] = {16'h110, 8'h3};
    assign reg_para[178] = {16'h111, 8'h0};
    assign reg_para[179] = {16'h112, 8'h0};
    
    assign reg_para[180] = {16'h113, 8'h0};
    assign reg_para[181] = {16'h114, 8'h0};
    assign reg_para[182] = {16'h115, 8'h0};
    assign reg_para[183] = {16'h116, 8'h30};
    assign reg_para[184] = {16'h118, 8'hf3};
    assign reg_para[185] = {16'h119, 8'h6};
    assign reg_para[186] = {16'h11a, 8'h0};
    assign reg_para[187] = {16'h11b, 8'h0};
    assign reg_para[188] = {16'h11c, 8'h0};
    assign reg_para[189] = {16'h11d, 8'h0};
    
    assign reg_para[190] = {16'h11e, 8'h0};
    assign reg_para[191] = {16'h11f, 8'h0};
    assign reg_para[192] = {16'h120, 8'h11};
    assign reg_para[193] = {16'h122, 8'hfd};
    assign reg_para[194] = {16'h123, 8'h0};
    assign reg_para[195] = {16'h124, 8'h3};
    assign reg_para[196] = {16'h125, 8'h0};
    assign reg_para[197] = {16'h126, 8'h0};
    assign reg_para[198] = {16'h127, 8'h0};
    assign reg_para[199] = {16'h128, 8'h0};
    
    assign reg_para[200] = {16'h129, 8'h0};
    assign reg_para[201] = {16'h12a, 8'h30};
    assign reg_para[202] = {16'h12c, 8'hf3};
    assign reg_para[203] = {16'h12d, 8'ha}; //CH10, gtx clk0 = 2500M / 10 = 250M
    assign reg_para[204] = {16'h12e, 8'h0};
    assign reg_para[205] = {16'h12f, 8'h0};
    assign reg_para[206] = {16'h130, 8'h0};
    assign reg_para[207] = {16'h131, 8'h0};
    assign reg_para[208] = {16'h132, 8'h0};
    assign reg_para[209] = {16'h133, 8'h0};
    
    assign reg_para[210] = {16'h134, 8'h11};
    assign reg_para[211] = {16'h136, 8'hf3};
    assign reg_para[212] = {16'h137, 8'h80}; //CH11 50 divide, cc0
    assign reg_para[213] = {16'h138, 8'h2};
    assign reg_para[214] = {16'h139, 8'h0};
    assign reg_para[215] = {16'h13a, 8'h0};
    assign reg_para[216] = {16'h13b, 8'h0};
    assign reg_para[217] = {16'h13c, 8'h0};
    assign reg_para[218] = {16'h13d, 8'h0};
    assign reg_para[219] = {16'h13e, 8'h30};
    
    assign reg_para[220] = {16'h140, 8'hf3};
    assign reg_para[221] = {16'h141, 8'ha}; //CH12 20 divide, gtx clk1 = 2500M / 10 = 250M
    assign reg_para[222] = {16'h142, 8'h0};
    assign reg_para[223] = {16'h143, 8'h0};
    assign reg_para[224] = {16'h144, 8'h0};
    assign reg_para[225] = {16'h145, 8'h0};
    assign reg_para[226] = {16'h146, 8'h0};
    assign reg_para[227] = {16'h147, 8'h0};
    assign reg_para[228] = {16'h148, 8'h11};
    assign reg_para[229] = {16'h14a, 8'hf3};
    
    assign reg_para[230] = {16'h14b, 8'h80}; //CH13 640 divide, cc2
    assign reg_para[231] = {16'h14c, 8'h2};
    assign reg_para[232] = {16'h14d, 8'h9};
    assign reg_para[233] = {16'h14e, 8'h0};
    assign reg_para[234] = {16'h14f, 8'h0};
    assign reg_para[235] = {16'h150, 8'h0};
    assign reg_para[236] = {16'h151, 8'h0};
    assign reg_para[237] = {16'h152, 8'h30};
    
    assign reg_para[238] = {16'h1, 8'h62};
    assign reg_para[239] = {16'h1, 8'h60};
    
    ///////////////////////////// HMC7044 config /////////////////////////////
    
    ///////////////////////////// JESD204 AXI config /////////////////////////////
    
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x008, 0x00000001);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x00C, 0x00000001);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x010, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x014, 0x00000003);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x018, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x020, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x024, 0x0000001F);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x028, 0x000000FF);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x02C, 0x00000001);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x80C, 0x00000000);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x810, 0x000F0F01);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x814, 0x00010101);
    usleep(1);
    write_memory(XPAR_JESD_204B_A_JESD204_0_BASEADDR + 0x818, 0x00000000);
    
    ///////////////////////////// JESD204 AXI config /////////////////////////////
    

    When FPGA keeps sending K28.5, it will also find sync going in and out, I tried to change lanerate(10G, 3G), but it also didn't work. Thank you!

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