Hello support team,
Now I'm designing Xilinx program as host for AD4000. That is, I'm trying to design for evaluation of EVAL-AD40XX-FMCZ with AC701. Now, I already have gotten the HDL design which is provided by ADI on the AD4000 product web page. There are design three '.v' files as following.(AD40XX-FPGA-Driver.zip)
- ADXX_data_capture.v -- sync_pulse.v (sub module of data capture) - ADXX_timing_gen.v
However there is not the design of top module for them in that page.So I would like to get the top module file, since I would like to know connection during each two modules.Also I would like to know the assigned external ports to total design.It is very helpful for my designing.
Do you have the top HDL(.v) design or its Vivado project? Also block diagram in top hieralkey is okey!