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Axi_dmac core. What is function of the fifo_wr_sync pin?

		
	
				

			

									
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				                on Dec 13, 2016 
				
			
			
		

		
		                    	    

        	    
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                The fifo_wr_sync pin in the AXI DMAC IP core is used for transfer start synchronization when configured with 'Transfer Start Synchronization Support'. It must be set to 1 along with fifo_wr_en to start data transfer. If not configured, it can be left unconnected or grounded. For 'Streaming AXI' source type, the function is handled by s_axis_user, requiring both s_axis_user and s_axis_valid to be 1 when s_axis_ready is 1.
                        	    

                
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What is function of the fifo_wr_sync pin of the axi_dmac ip core? Do i have to connect it to 1 or 0? When i have to use it and how?

 
Alex.

			

			
									
		                             
                        
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Dec 13, 2016 1:00 PM
            
            
						
			            		
    
		
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    Hello,
    
 
    If the IP is configured with the "Transfer Start Synchronization Support", after the DMA is configured it will start transferring data only after the fifo_wr_sync is 1 at the same time with fifo_wr_en.
    
 
    If you don't set that parameter, you can leave it unconnected / connected to ground.
    
 
    It is used for cases when data is transferred for more channels and the data corresponding to the first active channel is not the first data on the bus for each clock cycle.
    
 
    Regards,
    
 
    Adrian
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on May 15, 2017 8:50 PM
            
            
						
			            		
    
		
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    A further note that may save some additional head-scratching:
    
 
    If the DMA is configured to have DMA source type of "Streaming AXI", the function of the fifo_wr_sync pin is transferred to s_axis_user in the AXI-S interface.
    
 
    This means that both s_axis_user and s_axis_valid must be 1 when s_axis_ready is 1 for data to be transferred.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Aug 2, 2018 11:40 AM
            
            
						
			            		
    
		
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    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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