Controlling Breakout Carrier (PicoZed SDR) GPIOs

Hi,

Moved to FPGA reference designs. I believe those GPIOs are not actually mapped as GPIOs. See https://github.com/analogdevicesinc/hdl/blob/hdl_2016_r2/projects/pzsdr2/common/ccbrk_bd.tcl#L44-L47.

- Lars

Hi,

The GPIO pins that are available in software are connected by the gpio_bd net. Most of these have pre-defined functions like the push-buttons and LEDs, but other are general purpose and can be used freely.

Other pins can be made available by routing them to the gpio_bd net. But this requires changes to the constraints and system_top.v to update the number of mapped GPIO pins.

- Lars

Hi Lars,
I'm not sure I understand that .tcl. Do you mean there's not a single GPIO mapped to breakout carrier pins?

I just need 4 or 5 pins controllable from ARM, from either P4, P5, P6, P7, P2 or P13. How can I do it?

(Specially pins from Vcco_12 and Vcco_13 as we need 3.3 V)

Regards,
Leroy.

Hi,

My understanding is the same as yours. I'd expect them to be mapped at 971-974. Maybe somebody from the HDL team can shed some light on this.

- Lars

Forgive my ignorance, larsc. I always had trouble with I/O interfaces...

I'm not so sure what offset I should apply.

I found out first block of pins (pb, dip and leds) is between gpio960 and gpio971. This is an offset of 54, and kind of makes sense when looking at the devicetree. I'm able to play with them from ARM.

But with general purpose GPIOs (orphan ones?)  I don't know what offset I should apply as I can't find anything in devicetree. And they aren't either where I was expecting them to be (gpio971-gpio974, I can't even change their value to 1).

Regards,

Leroy.

Those pins (what Leroy highlighted above with yellow) can be controller through the axi_gpreg core, so there are not connected to the PS7's GPIO, rather to a axi gpio core.

I don't know anything about this core's linux support though.

What you can do, is simple reroute the unused PS7's GPIO (see the system_top.v) to your targeted pins, as Lars said above, and you're good.

-Istvan

The latest part of the discussion was about the "orphans- io-" pins. Which seem to be mapped to the to the PS7.

- Lars

I've noticed I compiled my design using dev branch a while ago, before 2016_R2 was released and this may be the problem. I think "ccbrk_constr.xdc" file didn't exist then, not even pzsdr2 folder.

I'm going to try and recompile everything from source code using last release and see what happens.

If you want something quick mmap() is probably OK.

Hi larsc and FormerMember ,

I've eventually managed to control all pins (yay!), either:

• using orphans pins (the problem was an old release was being used),
• rerouting other pins modifying XDC files as suggested (after learning a little about the inner workings of the design), 
• controlling axi_gpreg core from a Linux application by using mmap() and looking at its register addresses.

The last one seems to be the cleanest and fastest way to do it (also not having to edit the default picozed HDL sources). I just wonder... is it safe to access using mmap() to axi_gpreg registers?

Regards,
Leroy