Is there a reference manual, block diagram or similar for the ADI AXI DMA controller (and associated components) that is used in the FMCOMMS-2 reference HDL? I need to understand how the DMA controller is triggered, how and when the IRQ line is set, etc. for when the DMAC is operated in all three AXI, Memory-mapped and FIFO control modes. The wiki has plenty of good architecture information about the other IP blocks used in the design, but the DMAC seems to have very little documentation except the source code and I don't really want to have to trace the inputs, outputs and interrupt system by hand!
If there are any documents about how this block works, which unit is responsible for setting up the DMA channels, memory spaces etc. I'd really appreciate seeing a copy so I can begin to customize the design which I need to do for my application.
You can find a description of the register map at Base (common to all cores) - DMA Controller [Analog Devices Wiki]. Appart from that there is not much information available about the internal details. In general we recommend to use the ADI provided software drivers rather than re-implementing low-level access.