FMC DAQ2 SETUP

Dear all,

I'm working to setup the FMCDAQ2 (Hw an Sw) on KC705 board using the hdl-2016_r2 hardware  an no-OS-2016_R2 software, since I'm beginner in FPGA and sofware, thanks to your help I succeeded to take the first step. I get the debug running, I join here a short description, it could help beginners like myself. You told me that IIO oscilloscope application  will not work with bare-metall no-os software.
My question are there any tutorial or guide that explains easily how to write data and read data  from the memory,
just simple example put data and capture it .. Rejeesh gave this https://github.com/analogdevicesinc/no-OS/blob/2016_R2/scripts/capture.tcl
where can I source it, it seems in the debugger, can I also write a data file into the memory ?
thanks very much

NOOS_2016_R2.pdf
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  • Did you define the PATH for Vivado and for SDK on your .bashrc file?

    About the second questions:

    A) The reference software has the following process: 

         - define all the configuration (clocking device, DAC device, ADC device, FPGA tranceivers/jesd/device cores and DMAs)

         - setup GPIO (bring up everybody from reset)

         - setup the AD9523 (after this all the clocks are up and running)

         - setup JESD cores in FPGA

         - setup the GTs (Gigabit Transceivers) in FPGA

         - setup the device cores in FPGA

         - test the transmit path with pre-defined pattern and PRBS sequence

         - test the receive path with PRBS sequence 

         - setup and start transmission; data generated by DDS or data from memory (TX_DMA); the transmission is free running

         - receive transmitted data (RX_DMA captures a predefined number of samples and stops)

         - end of software

    The number of received samples are defined here: no-OS/fmcdaq2.c at 2016_R2 · analogdevicesinc/no-OS · GitHub  This value should be the same as the capture size, defined in microblaze.mk.

Reply
  • Did you define the PATH for Vivado and for SDK on your .bashrc file?

    About the second questions:

    A) The reference software has the following process: 

         - define all the configuration (clocking device, DAC device, ADC device, FPGA tranceivers/jesd/device cores and DMAs)

         - setup GPIO (bring up everybody from reset)

         - setup the AD9523 (after this all the clocks are up and running)

         - setup JESD cores in FPGA

         - setup the GTs (Gigabit Transceivers) in FPGA

         - setup the device cores in FPGA

         - test the transmit path with pre-defined pattern and PRBS sequence

         - test the receive path with PRBS sequence 

         - setup and start transmission; data generated by DDS or data from memory (TX_DMA); the transmission is free running

         - receive transmitted data (RX_DMA captures a predefined number of samples and stops)

         - end of software

    The number of received samples are defined here: no-OS/fmcdaq2.c at 2016_R2 · analogdevicesinc/no-OS · GitHub  This value should be the same as the capture size, defined in microblaze.mk.

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