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Xilinx JESD core vs. ADI JESD core

Hi all,

Hoping someone could clear something up for me... Working with the AD9371, and ADI has developed a whole slew of JESD204 interface cores, specifically:

  1. axi_adxcvr_v1_0
  2. util_adxcvr_v1_0
  3. ADI JESD204B Receive AXI Interface
  4. ADI JESD204 Receive
  5. ADI JESD204B Transmit AXI Interface
  6. ADI JESD204 Transmit

What is the recommendation in terms of using these vs. the Xilinx JESD PHY and core? I already have the Xilinx license, so cost isn't relevant to this particular application.

  • Dear all,

    We've got a similar question of choosing between ADI JESD IP and Xilinx JESD IP.

    Again, the cost is not an issue.

    Could someone provide advices about the pros and cons, please?

    Especially, does the ADI core capable of supporting deterministic latency and synchronising multiple converters (without significantly altering the code), assuming the hardware design meets the specification of the JESD204B, sub1.

    Thanks a lot.



  • Hi Wade,

    we do not have a one to one detailed comparison available.

    The ADI cores:

    + support deterministic latency with Subclass 1, in all modes including N'=12, or F>4;

    + support multiple links, can combine multiple parts (see quad MxF hdl for ADQUADMXFE board)

    + supports 204C  64b66b mode.

    + you have access to the source code

    + has Transport Layer for Rx and Tx paths

    + for Rx it has support for 2D eye scan

    + has complete Linux and no-os software support

    + has free EngineerZone support

    + was validated with a large variety of ADI parts

    + supports also Intel platforms

    + link layer is Xilinx platform agnostic,supports Versal

    + ADI phy supports most Xilinx transceivers, if not, link layer can interface with Xilinx PHY

    - may be used only with ADI parts

    For more details consult the documentation of the framework :

    Thank you,


  • Hi Wade,

     I have a custom AD9136 DAC design which I have setup both Xilinx and Analog Devices JESD204 IP builds for.

     Part of my design generates high speed Marker outputs with 1ns resolution that align with the DAC outputs. With the Analog Devices JESD204 after power cycles the Maker outs and DAC output are sometimes up to 2ns off from each other. With the Xilinx JESD204 the Makers and DAC always appear to be aligned with each other after power cycles. A was never able to understand how to fix the issue.

     I am not sure about syncing multiple parts, there are syncing signals that are produced by the common clock gen. You should look over the ADQADMXFE to see how it is done. 

     The nice thing about the Analog Devices JESD204 is it direct supported in their base HDL designs and Linux Drivers.

     You can read the HDL IP code Analog Devices has for JESD204.

     One of the things with the Xilinx JESD204B is you must have an IP license to build bitstream in Vivado tool. You have to buy extended license after a year to support new versions of Vivado. The Analog Devices JESD204 IP on the other hand only requires a usage fee for end commercial product at $5,000. See JESD204 Interface Framework | Design Center | Analog Devices. I am not sure if they waver the fee if you use their parts. 


  • Hi Laszlo

    Thanks for the comment.

    I'm wondering if the support of synchronizing multiple chips is available for the ADI core, after purchasing it.

    Best regards,


  • Hi Jay,

    Thanks for the comment.

    I'm not quite sure I followed this "ADQADMXFE", there is probably a typo.

    Do you mean FMCDAQ or some other board? Thanks.

    Best regards,


  • Hi Wade,

    synchronizing multiple chips is supported.

    For reference see how it was used for the QUADMXFE design.


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