Hi all,
Hoping someone could clear something up for me... Working with the AD9371, and ADI has developed a whole slew of JESD204 interface cores, specifically:
What is the recommendation in terms of using these vs. the Xilinx JESD PHY and core? I already have the Xilinx license, so cost isn't relevant to this particular application.
Hi ,
I am using a VCXO of 80MHz generating a device clock of 80MHz (9528 is redundant in my case yet still I am using it) that is used as reference in both AD9371 and FPGA transceivers. the transceivers lane rate is 3.2GHz.
On the AD9371 I use a VCO=9.6GHz and divide by 3 to generate the 3.2GHz lane rate:
static mykonosDigClocks_t mykonosClocks =
{
80000, /* CLKPLL and device reference clock frequency in kHz*/
9600000, /* CLKPLL VCO frequency in kHz*/
VCODIV_3, /* CLKPLL VCO divider*/
5 /* CLKPLL high speed clock divider*/
};
static mykonosRxProfile_t rxProfile =
{/* RX 80MHz, Iqrate 160MSPS, DEC5 */
1, /* The divider used to generate the ADC clock*/
&rxFir, /* Pointer to Rx FIR filter structure*/
1, /* Rx FIR decimation (1,2,4)*/
4, /* Decimation of Dec5 or Dec4 filter (5,4)*/
0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
1, /* RX Half band 1 decimation (1 or 2)*/
160000, /* Rx IQ data rate in kHz*/
80000000, /* The Rx RF passband bandwidth for the profile*/
80000, /* Rx BBF 3dB corner in kHz*/
&rxAdcCustom[0] /* pointer to custom ADC profile*/
};
On the FPGA side the XCVR block generates the 3.2GHz using the CPLL.
After initialization and bypassing of few AGC and TXIQC calibration related errors I get :
Please wait...
RX_XCVR initialization OK
TX_XCVR initialization OK
RX_OS_XCVR initialization OK
MCS successful
CLKPLL locked
AD9371 ARM version 5.1.1
PLLs locked
Calibrations completed successfully
DeframerStatus = 0x61
dac_setup dac core initialized (160 MHz).
adc_setup adc core initialized (160 MHz).
Done
when using the ILA to view the rx clock and rxos generators output I see completely random wave forms as shown below. What am I doing wrong ?
Hi ,
I am using a VCXO of 80MHz generating a device clock of 80MHz (9528 is redundant in my case yet still I am using it) that is used as reference in both AD9371 and FPGA transceivers. the transceivers lane rate is 3.2GHz.
On the AD9371 I use a VCO=9.6GHz and divide by 3 to generate the 3.2GHz lane rate:
static mykonosDigClocks_t mykonosClocks =
{
80000, /* CLKPLL and device reference clock frequency in kHz*/
9600000, /* CLKPLL VCO frequency in kHz*/
VCODIV_3, /* CLKPLL VCO divider*/
5 /* CLKPLL high speed clock divider*/
};
static mykonosRxProfile_t rxProfile =
{/* RX 80MHz, Iqrate 160MSPS, DEC5 */
1, /* The divider used to generate the ADC clock*/
&rxFir, /* Pointer to Rx FIR filter structure*/
1, /* Rx FIR decimation (1,2,4)*/
4, /* Decimation of Dec5 or Dec4 filter (5,4)*/
0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
1, /* RX Half band 1 decimation (1 or 2)*/
160000, /* Rx IQ data rate in kHz*/
80000000, /* The Rx RF passband bandwidth for the profile*/
80000, /* Rx BBF 3dB corner in kHz*/
&rxAdcCustom[0] /* pointer to custom ADC profile*/
};
On the FPGA side the XCVR block generates the 3.2GHz using the CPLL.
After initialization and bypassing of few AGC and TXIQC calibration related errors I get :
Please wait...
RX_XCVR initialization OK
TX_XCVR initialization OK
RX_OS_XCVR initialization OK
MCS successful
CLKPLL locked
AD9371 ARM version 5.1.1
PLLs locked
Calibrations completed successfully
DeframerStatus = 0x61
dac_setup dac core initialized (160 MHz).
adc_setup adc core initialized (160 MHz).
Done
when using the ILA to view the rx clock and rxos generators output I see completely random wave forms as shown below. What am I doing wrong ?
