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AD9371 Recommended for New Designs
The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal...
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Xilinx JESD core vs. ADI JESD core

		
	
				

			

									
					    CodeWarrior
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 3, 2017 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi all,
    
 
    Hoping someone could clear something up for me... Working with the AD9371, and ADI has developed a whole slew of JESD204 interface cores, specifically:
    
 
      
  
    1. axi_adxcvr_v1_0
      2. 
  
    2. util_adxcvr_v1_0
      3. 
  
    3. ADI JESD204B Receive AXI Interface
      4. 
  
    4. ADI JESD204 Receive
      5. 
  
    5. ADI JESD204B Transmit AXI Interface
      6. 
  
    6. ADI JESD204 Transmit
      7. 
 
    
 
    What is the recommendation in terms of using these vs. the Xilinx JESD PHY and core? I already have the Xilinx license, so cost isn't relevant to this particular application.
    
			
    
			
									
		                             
                        

    
    
                                            
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jul 4, 2017 7:31 AM
            
            
						
			            		
      
		
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      Our ultimate goal is to use the ADI JESD IP core in conjunction with the Xilinx PHY. In the next release (hdl_2017_r1) the ADI JESD IP core will be adopted (that is what you see in the dev branch now). After that (hdl_2017_r2), we will integrate the Xilinx PHY too.
      
 
      So in the future we going to support the combination mentioned above. And in all our future developments, we are going to use those IPs.
      
 
      Thanks,
      
 
      -Istvan
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jul 4, 2017 7:31 AM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Our ultimate goal is to use the ADI JESD IP core in conjunction with the Xilinx PHY. In the next release (hdl_2017_r1) the ADI JESD IP core will be adopted (that is what you see in the dev branch now). After that (hdl_2017_r2), we will integrate the Xilinx PHY too.
      
 
      So in the future we going to support the combination mentioned above. And in all our future developments, we are going to use those IPs.
      
 
      Thanks,
      
 
      -Istvan
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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