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Xilinx JESD core vs. ADI JESD core

Hi all,

Hoping someone could clear something up for me... Working with the AD9371, and ADI has developed a whole slew of JESD204 interface cores, specifically:

  1. axi_adxcvr_v1_0
  2. util_adxcvr_v1_0
  3. ADI JESD204B Receive AXI Interface
  4. ADI JESD204 Receive
  5. ADI JESD204B Transmit AXI Interface
  6. ADI JESD204 Transmit

What is the recommendation in terms of using these vs. the Xilinx JESD PHY and core? I already have the Xilinx license, so cost isn't relevant to this particular application.

  • Our ultimate goal is to use the ADI JESD IP core in conjunction with the Xilinx PHY. In the next release (hdl_2017_r1) the ADI JESD IP core will be adopted (that is what you see in the dev branch now). After that (hdl_2017_r2), we will integrate the Xilinx PHY too.

    So in the future we going to support the combination mentioned above. And in all our future developments, we are going to use those IPs.



  • Does ADI have a preliminary schedule for 2017_r1 and 2017_r2 release, so that we can look out for that? Or is that published somewhere and I just don't know it?

  • All our repositories are public. The dev branch is our development branch, so everything that you see on dev will be in the next release. In general our target is to do two release annually. The 2017_r1 will be made in the next few weeks, 2017_r2 is expected at the end of this year.

  • Hi ,

    I am using a VCXO of 80MHz generating a device clock of 80MHz (9528 is redundant in my case yet still I am using it) that is used as reference in both AD9371 and FPGA transceivers. the transceivers lane rate is 3.2GHz.

    On the AD9371 I use a VCO=9.6GHz and divide by 3 to generate the 3.2GHz lane rate:

    static mykonosDigClocks_t mykonosClocks =
    80000, /* CLKPLL and device reference clock frequency in kHz*/
    9600000, /* CLKPLL VCO frequency in kHz*/
    VCODIV_3, /* CLKPLL VCO divider*/ 
    5 /* CLKPLL high speed clock divider*/

    static mykonosRxProfile_t rxProfile =
    {/* RX 80MHz, Iqrate 160MSPS, DEC5 */
    1, /* The divider used to generate the ADC clock*/
    &rxFir, /* Pointer to Rx FIR filter structure*/
    1, /* Rx FIR decimation (1,2,4)*/
    4, /* Decimation of Dec5 or Dec4 filter (5,4)*/
    0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
    1, /* RX Half band 1 decimation (1 or 2)*/
    160000, /* Rx IQ data rate in kHz*/
    80000000, /* The Rx RF passband bandwidth for the profile*/
    80000, /* Rx BBF 3dB corner in kHz*/
    &rxAdcCustom[0] /* pointer to custom ADC profile*/

    On the FPGA side the XCVR block generates the 3.2GHz using the CPLL. 

    After initialization and bypassing of few AGC and TXIQC calibration related errors I get :

    Please wait...
    RX_XCVR initialization OK
    TX_XCVR initialization OK
    RX_OS_XCVR initialization OK
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.1.1
    PLLs locked
    Calibrations completed successfully
    DeframerStatus = 0x61
    dac_setup dac core initialized (160 MHz).
    adc_setup adc core initialized (160 MHz).

    when using the ILA to view the rx clock and rxos generators output I see completely random wave forms as shown below. What am I doing wrong ? 

  • Your question is posted here: too. We'll continue the discussion on the other thread.



  • question pending in the new thread. 

    thanks Dragos.

  • Dear all,

    We've got a similar question of choosing between ADI JESD IP and Xilinx JESD IP.

    Again, the cost is not an issue.

    Could someone provide advices about the pros and cons, please?

    Especially, does the ADI core capable of supporting deterministic latency and synchronising multiple converters (without significantly altering the code), assuming the hardware design meets the specification of the JESD204B, sub1.

    Thanks a lot.



  • Hi Wade,

    we do not have a one to one detailed comparison available.

    The ADI cores:

    + support deterministic latency with Subclass 1, in all modes including N'=12, or F>4;

    + support multiple links, can combine multiple parts (see quad MxF hdl for ADQUADMXFE board)

    + supports 204C  64b66b mode.

    + you have access to the source code

    + has Transport Layer for Rx and Tx paths

    + for Rx it has support for 2D eye scan

    + has complete Linux and no-os software support

    + has free EngineerZone support

    + was validated with a large variety of ADI parts

    + supports also Intel platforms

    + link layer is Xilinx platform agnostic,supports Versal

    + ADI phy supports most Xilinx transceivers, if not, link layer can interface with Xilinx PHY

    - may be used only with ADI parts

    For more details consult the documentation of the framework :

    Thank you,


  • Hi Wade,

     I have a custom AD9136 DAC design which I have setup both Xilinx and Analog Devices JESD204 IP builds for.

     Part of my design generates high speed Marker outputs with 1ns resolution that align with the DAC outputs. With the Analog Devices JESD204 after power cycles the Maker outs and DAC output are sometimes up to 2ns off from each other. With the Xilinx JESD204 the Makers and DAC always appear to be aligned with each other after power cycles. A was never able to understand how to fix the issue.

     I am not sure about syncing multiple parts, there are syncing signals that are produced by the common clock gen. You should look over the ADQADMXFE to see how it is done. 

     The nice thing about the Analog Devices JESD204 is it direct supported in their base HDL designs and Linux Drivers.

     You can read the HDL IP code Analog Devices has for JESD204.

     One of the things with the Xilinx JESD204B is you must have an IP license to build bitstream in Vivado tool. You have to buy extended license after a year to support new versions of Vivado. The Analog Devices JESD204 IP on the other hand only requires a usage fee for end commercial product at $5,000. See JESD204 Interface Framework | Design Center | Analog Devices. I am not sure if they waver the fee if you use their parts. 


  • Recommendation is to start with an AD FPGA reference design matching your FPGA. (better to have a zynq) for JESD204 configuration. i did it on a Microblaze today :)