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I want to port the ML605 LVDS code to Zynq. I only want to use the LVDS data acquisition and not DMA. Please help.

I am trying to use the AD9278 with Zynq and have downloaded the reference design ML605. I can see that there's a DMA interface in the code. However, I am not able to find SPI interface for configuration, and I have implemented that. 

I also would like to use the LVDS data acquisition from the reference design in ZYNQ. I do not understand what sections do I have to use. Also, if the bit alignment routine is running all the time, it seems to be based on the PN sequence. For this, I think the PN sequence test would have to be enabled in the AFE. I think this is done via the PC utility, but in my case, I guess I will have to do it via the FPGA. Please help me to understand what part of the reference code I need to use.

  • You need to first understand that design before proceeding.

    It has a SPI interface and does configure that part.

    If you can specify what part of the design (assuming not all of it) is confusing, we will try to explain.

  • SPI is okay, I guess I was able to manage that. 

    However, I had made a custom module to read data over LVDS, but wasn't working very well when I came across the reference design that is available. 

    In the design I can see that the data is acquired over LVDS and then sent to the RAM. However, I am unable to understand:

    1. What signals are used to start a conversion (or acquire data assuming that the AFE is sampling continuously)

    2. Which signal do I check to read the data after a conversion (something like a "done" signal), say if I want to capture one sample

    3. How's the PN sequence bit alignment really working? I am assuming that the SPI initially enables the PN test mode in the AFE and then acquires data to complete the bit alignment, but not sure!

    I am using the files available at cf_ad9279_ebz_edk_14_4_2013_03_26.tar.gz.

    Got them downloaded from https://wiki.analog.com/resources/fpga/xilinx/interposer/ad9279

    I thank you in advance for the help!

  • 1. In our design - nothing, it just an arbitrary point in time DMA is started and at that point it writes then samples to DDR. However, I do believe there is a external trigger on this hardware, but this requires some changes so that you initiate the DMA but capture is only started with trigger.

    2. The core simply outputs samples, if you need the trigger use it to look at the output.

    3. There is a test mode in the device, if it is enabled it will send PRBS data instead of samples. Look for it in the data sheet.