NOTE: I moved this question from high-speed DACs to this section at the suggestion of Chris
I need some general questions answered about the AD9739A and its eval board, the AD9739a-FMC-EBZ.
Background:I have one of these attached to a zedboard. I built the HDL and software for the ZC706, learned what it is doing then ported it some of it to the zedboard. For the HDL part, I am only using the ad9739a_if.v and below, I am feeding its 256-bit bus with my own module. This placed fine and is running on the ZED FPGA fabric. I implemented the SPI control path on my own, and I am able to read and write the SPI registers on the EBZ. The clock chip lights it lock LED after being programmed. I can read and write the DACs SPI registers. The default register values come back from the DAC and match the values in the DS (rev D).
As for software, I am using the modules needed to program the clock and DAC chips through the SPI interface. The eval project was self-explanitory and easy to use.
Using the default settings in the eval, which match the DAC data sheet, I am not getting Mu lock
1. I am having trouble understanding the procedure for setting slope and delay based on the dac_clk. Looking at fig 166 in the data sheet, it looks like MU_DELAY of 216 is near the negative slope of 6 "desired phase" point. The Mu controller will search for this point on its own. I dont understand how changing the clock input rate will change this decision logic. Is ADI implying that the wave in fig 166 will spread out as the freq goes down? Doesn't the Mu delay value LSB value change as the clock freq does, the Mu logic is clocked by the same clock it is measuring. I think I am missing a key point.
2. In this forum post: https://ez.analog.com/message/223029, evandavis sez he is setting the dac_clk to 1Gsps. The data sheet specifies the DAC_CLK input as having a range of 1.6 to 2.5 GHz. How does this work, I am asking because:
3. I too want to use this DAC as a baseband DAC, clock it in the range of 200MHz. This question: https://ez.analog.com/docs/DOC-14353 asks just this. if I set the input clock to 200MHz, will the DAC be able to handle this. I dont undertand how you can use a DAC_CLK of 2.5GHz with an FPGA. This means a 625MHz DCO!Can you suggest DAC register settings to handle this?
4. the person that responded to analog-archivist said "This will work to some degree. The throughput and full capability of the AD9739A is somewhat quite limited when using with ZED Board". Can I get a better explanation than "some degree" and "quite limited".The zedboard has all the correct connections to attach to the EBZ. I dont kno who responded to the question or I could ask them...
5. What does the DCO look like if the Mu controller does not lock? I can change the clock chip output but I always get the same DCO from the 9739. It varies so much it looks like a data line!
6. Is the A3 (3.3v) VR supposed to get hot?
The AD9739A will not work with a DAC clock of 200 MHz. This is the reason that the mu controller is not locking. You must supply a DAC clock frequency of at least 1600 MHz for the mu controller to lock.
Thanks for the reply! I am not getting Mu lock at any dac_clk freq. I set the ebz up using the ADI supplied settings (that came with the github code) initially. Part of its init is to turn on the Mu controller and wait for it to "lock". I never see it lock. I tried several other clock freqs with the same result. I also tried an array of phases and delay values to no avail. I see the clock chip being programmed and see the clock change. I don't have a scope that can show 2.5GHz, but I see a change in the dac_clk signal when the programming is done. the clock chips lock LED is on. This is all I have to troubleshoot with.
As far as the DAC, with the board powered up, and the DAC programmed using the code off github, the Mu controller does not lock, and the clock output (DCO) looks like junk. It is transitioning through the correct voltage levels but it actually looks like a data line, there is no hint of a single frequency.
I set the dac_clk to 1.6GHz, the DCO should be 400MHz, which I can see with my scope. I get the same jibberish on the DCO. What is the DCO signal supposed to look like before and after the DAC chip is programmed?
Incidentially, why were the jumpers not installed on the EBZs JP1 and JP2? Without these jumpered, the board has no power!
I can't really say much without seeing your design.
We don't use ZED, because the rate is too high (7020 is limited to 464MHz).
You may still be able to overclock it, but I am not sure.
I would try with a BUFIO/BUFR combination on ZED.
I have been communicating with Chris about the actual DAC and its settings. There is either a bug in the setup code on github or the DAC on my EBZ is bad. I have extensively gone over the init code for the DAC and it is getting the correct values as per the DS. The code on github matches the DS. I'm leaning towards a bad DAC.
I don't think there is a problem using the zedboard, if you set the clock to 1.6GHz, the DCO should be 400MHz, but I am not seeing a DCO that looks anything like a clock. The HDL design I got from github as proper Xilinx clocking components instantiated for this situation.
As for the AD9739A_FMC_EBZ, who supports the board itself? I still have these two outstanding questions about this board:
1. Why were the jumpers not installed on the EBZs JP1 and JP2? There is no mention of this in the wiki. The parts need these installed to power up!
2. Is the A3 (3.3v) VR supposed to get hot?
I am a bit confused, the default sets up the clock chip around 2.4G and runs DCO at 600M.
So you should not be using that setup, we do not have a setup to run at 1.6G (IIRC it uses ADF4355).
Anyway, if you have managed to bring it down to 1.6G, you should be fine.
I will check on the hardware support and answers to those two questions.