Problem in bit file generation

I'm using a 32 bit OS so I installed vivado 2014.4.1 version and I'm using zc7020 zynq 7000 FPGA. I've also using hdl-2015_r1 as provided here:

I followed the steps provided by ADI website:

While running the project I got an error stating axi_clkgen is not supported for this tool. I also found the engineer zone thread discussing this problem:

So, I added a simulation clock generator from "Add IP" option from create a design block under Integrator.

After that I can able to run the synthesis part, but in implementation part under placer i'm facing the placer errors whose snapshots are attached below,

Is this proper method or what can I do to generate the bit ?