Your question indicates that you haven't done much home work. Other than trying to match AD9144 with AD9744 (they are just one character different in name doesn't mean anything).
To answer your point, you will implement 14 bit registers at 210 MHz (with whatever you want as samples feeding them). You can implement these registers as ODDR with same data line driving both rising & falling edge registers.
Requesting some additional info on this old thread - I am trying to implement AD9744 interface in Zynq FPGA. Looking at the timing diagram (Fig.2) in the AD9744 data-sheet, the DB lines just need to meet the setup and hold time w.r.t. the rising edge of the clock. There is also a suggestion in the data-sheet to have data driven on the falling edge of the clock.
I have the following questions:
1. Why is an ODDR register suggested in this case, with both rise-edge and fall-edge data inputs to ODDR driven by the same data line. Can't it not be simple posedge clock based data-registers driving the FPGA pins going to the ribbon connector ?
2. Is there a sample VHDL/Verilog code implementing the ODDR register based DB input to AD9744 eval board.
3. There are two types of ODDR implementation : Same Edge mode (both edges capture data) and Opposite edge mode (data captured only on positive edge). Is it the Same Edge mode suggested here ?
4. As far as the delay in clock and DB propagation, is there any mechanism to tune the relative arrival times ?
Thanks in advance for the help.
Replied at https://ez.analog.com/fpga/f/q-a/117254/ad9744acp-pcbz-dac-board-clock-and-data